• KIISE Transactions on Computing Practices
• /
• v.23 no.2
• /
• pp.97-103
• /
• 2017

Many hardware-based regular expression matching architectures have been proposed for high-performance matching. In particular, regular expression processors, which perform pattern matching by treating the regular expressions as the instruction sequence like general purpose processors, have been proposed. After instruction sequence and data are provided in the instruction memory and data memory, respectively, a regular expression processor can perform pattern matching. To use a regular expression processor as a coprocessor, we need the host interface to transfer the instruction and data into the memory of a regular expression processor. In this paper, we design and implement the host interface between a host and a regular expression processor in the DE1-SoC board and the application program interface. We verify the operations of the host interface and a regular expression processor by executing the application programs which perform pattern matching using the application program interface.

• Design & Manufacturing
• /
• v.16 no.3
• /
• pp.34-38
• /
• 2022

Regular expression pattern matching is widely used in applications such as computer virus vaccine, NIDS and DNA sequencing analysis. Hardware-based pattern matching is used when high-performance processing is required due to time constraints. ReCPU, SMPU, and REMP, which are processor-based regular expression matching processors, have been proposed to solve the problem of the hardware-based method that requires resynthesis whenever a pattern is updated. However, these processor-based regular expression matching processors inefficiently handle repetitive operations of regular expressions. In this paper, we propose a new instruction set to improve the inefficient repetitive operations of ReCPU and SMPU. We propose REMPi, a regular expression matching processor that enables efficient iterative operations based on the REMP instruction set. REMPi improves the inefficient method of processing a particularly short sub-pattern as a repeat operation OR, and enables processing with a single instruction. In addition, by using a down counter and a counter stack, nested iterative operations are also efficiently processed. REMPi was described with Verilog and synthesized on Intel Stratix IV FPGA.

• Journal of Computing Science and Engineering
• /
• v.8 no.2
• /
• pp.78-86
• /
• 2014

Aiming to solve the problems of high memory access and big storage space and long matching time in the regular expression matching of extended finite automaton (XFA), a new regular expression matching algorithm based on high-efficient finite automaton is presented in this paper. The basic idea of the new algorithm is that some extra judging instruments are added at the starting state in order to reduce any unnecessary transition paths as well as to eliminate any unnecessary state transitions. Consequently, the problems of high memory access consumption and big storage space and long matching time during the regular expression matching process of XFA can be efficiently improved. The simulation results convey that our proposed scheme can lower approximately 40% memory access, save about 45% storage space consumption, and reduce about 12% matching time during the same regular expression matching process compared with XFA, but without degrading the matching quality.

• Journal of IKEEE
• /
• v.22 no.1
• /
• pp.87-92
• /
• 2018

Like CPUs, regular expression processors that perform regular expression pattern matching using instructions have been proposed recently. Of these, only REMPc provides features for character class matching. In this paper, we propose an architecture for efficient character class matching in a regular expression processor, which use character class bitmap format in a instruction operand field and implement the hard-wired character class comparator for several frequently used character classes. Using the proposed method, most of the character classes used in Snort rule can be represented by an operand or an instruction. Thus, character class matching can be performed more efficiently in the proposed archiecture than in REMPc.

• Journal of KIISE
• /
• v.42 no.10
• /
• pp.1280-1285
• /
• 2015

Many hardware-based regular expression matching architectures are proposed for high performance matching. In particular, regular expression processors such as ReCPU and SMPU perform pattern matching in a similar approach to that used in general purpose processors, which provide the flexibility when updating patterns. However, these processors are inefficient in performing class matching since they do not provide character class matching capabilities. This paper proposes an instruction set and architecture of a regular expression matching processor, which can support character class matching. The proposed processor can efficiently perform character class matching since it includes character class, character range, and negated character class matching capabilities.

• Proceedings of the KIEE Conference
• /
• 1986.07a
• /
• pp.486-489
• /
• 1986

The transition diagram, as well as the regular expression, can be used as a formal description for a language acceptable by a finite automaton or for the behavior of a sequential switching circuit. But, if we are given one of these two descriptions, we shall find that it is not easy to get the other counterpart description. This paper is to show an easy method to find the equivalet regular expression from the transition diagram, by the aid of a graph-transformation technique.

• Journal of the Korea Society of Computer and Information
• /
• v.16 no.5
• /
• pp.13-22
• /
• 2011

Network Intrusion Detection Systems use regular expression to represent malicious packets and hardware-based pattern matching is required for fast deep packet inspection. Although hardware architectures for implementing constraint repetition operators such as {10} were recently proposed, they have some limitation. In this paper, we propose hardware architecture supporting constraint repetitions of general regular expression sub-patterns with lower logic complexity. The subpatterns supported by the proposed contraint repetition architecture include general regular expression patterns as well as a single character and fixed length patterns. With the proposed building block, we can implement more efficiently regular expression pattern matching hardwares.

• Journal of Information Processing Systems
• /
• v.19 no.1
• /
• pp.1-16
• /
• 2023

Synthetic data generation is generally used in performance evaluation and function tests in data-intensive applications, as well as in various areas of data analytics, such as privacy-preserving data publishing (PPDP) and statistical disclosure limit/control. A significant amount of research has been conducted on tools and languages for data generation. However, existing tools and languages have been developed for specific purposes and are unsuitable for other domains. In this article, we propose a regular expression-based data generation language (DGL) for flexible big data generation. To achieve a general-purpose and powerful DGL, we enhanced the standard regular expressions to support the data domain, type/format inference, sequence and random generation, probability distributions, and resource reference. To efficiently implement the proposed language, we propose caching techniques for both the intermediate and database queries. We evaluated the proposed improvement experimentally.

• Journal of applied mathematics & informatics
• /
• v.27 no.1_2
• /
• pp.409-417
• /
• 2009

A definition of finite automaton (DFA and NDFA) with intuitionistic fuzzy (final) states is proposed. Acceptance of intuitionistic fuzzy regular language by the finite automaton (DFA and NDFA) with intuitionistic fuzzy (final) states are examined. It is found that the finite automaton (DFA and NDFA) with intuitionistic fuzzy (final) states is more suitable for recognizing intuitionistic fuzzy regular language than earlier model. The paper also gives an idea of intuitionistic fuzzy regular expressions through possible definitions.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.1B
• /
• pp.47-55
• /
• 2009

In recent network intrusion detection systems, regular expressions are used to represent malicious packets. In order to process incoming packets through high speed networks in real time, we should perform hardware-based pattern matching using the configurable device such as FPGAs. However, operating speed of FPGAs is slower than giga-bit speed network and so, multi-byte processing per clock cycle may be needed. In this paper, we propose a hardware architecture of multi-byte based regular expression pattern matching and implement the pattern matching circuit generator. The throughput improvements in four-byte based pattern matching circuit synthesized in FPGA for several Snort rules are $2.62{\sim}3.4$ times.