• Title/Summary/Keyword: Reference Signal

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A Polarization-based Frequency Scanning Interferometer and the Measurement Processing Acceleration based on Parallel Programing (편광 기반 주파수 스캐닝 간섭 시스템 및 병렬 프로그래밍 기반 측정 고속화)

  • Lee, Seung Hyun;Kim, Min Young
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.8
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    • pp.253-263
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    • 2013
  • Frequency Scanning Interferometry(FSI) system, one of the most promising optical surface measurement techniques, generally results in superior optical performance comparing with other 3-dimensional measuring methods as its hardware structure is fixed in operation and only the light frequency is scanned in a specific spectral band without vertical scanning of the target surface or the objective lens. FSI system collects a set of images of interference fringe by changing the frequency of light source. After that, it transforms intensity data of acquired image into frequency information, and calculates the height profile of target objects with the help of frequency analysis based on Fast Fourier Transform(FFT). However, it still suffers from optical noise on target surfaces and relatively long processing time due to the number of images acquired in frequency scanning phase. 1) a Polarization-based Frequency Scanning Interferometry(PFSI) is proposed for optical noise robustness. It consists of tunable laser for light source, ${\lambda}/4$ plate in front of reference mirror, ${\lambda}/4$ plate in front of target object, polarizing beam splitter, polarizer in front of image sensor, polarizer in front of the fiber coupled light source, ${\lambda}/2$ plate between PBS and polarizer of the light source. Using the proposed system, we can solve the problem of fringe image with low contrast by using polarization technique. Also, we can control light distribution of object beam and reference beam. 2) the signal processing acceleration method is proposed for PFSI, based on parallel processing architecture, which consists of parallel processing hardware and software such as Graphic Processing Unit(GPU) and Compute Unified Device Architecture(CUDA). As a result, the processing time reaches into tact time level of real-time processing. Finally, the proposed system is evaluated in terms of accuracy and processing speed through a series of experiment and the obtained results show the effectiveness of the proposed system and method.

A development of DS/CDMA MODEM architecture and its implementation (DS/CDMA 모뎀 구조와 ASIC Chip Set 개발)

  • 김제우;박종현;김석중;심복태;이홍직
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.6
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    • pp.1210-1230
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    • 1997
  • In this paper, we suggest an architecture of DS/CDMA tranceiver composed of one pilot channel used as reference and multiple traffic channels. The pilot channel-an unmodulated PN code-is used as the reference signal for synchronization of PN code and data demondulation. The coherent demodulation architecture is also exploited for the reverse link as well as for the forward link. Here are the characteristics of the suggested DS/CDMA system. First, we suggest an interlaced quadrature spreading(IQS) method. In this method, the PN coe for I-phase 1st channel is used for Q-phase 2nd channels and the PN code for Q-phase 1st channel is used for I-phase 2nd channel, and so on-which is quite different from the eisting spreading schemes of DS/CDMA systems, such as IS-95 digital CDMA cellular or W-CDMA for PCS. By doing IQS spreading, we can drastically reduce the zero crossing rate of the RF signals. Second, we introduce an adaptive threshold setting for the synchronization of PN code, an initial acquistion method that uses a single PN code generator and reduces the acquistion time by a half compared the existing ones, and exploit the state machines to reduce the reacquistion time Third, various kinds of functions, such as automatic frequency control(AFC), automatic level control(ALC), bit-error-rate(BER) estimator, and spectral shaping for reducing the adjacent channel interference, are introduced to improve the system performance. Fourth, we designed and implemented the DS/CDMA MODEM to be used for variable transmission rate applications-from 16Kbps to 1.024Mbps. We developed and confirmed the DS/CDMA MODEM architecture through mathematical analysis and various kind of simulations. The ASIC design was done using VHDL coding and synthesis. To cope with several different kinds of applications, we developed transmitter and receiver ASICs separately. While a single transmitter or receiver ASC contains three channels (one for the pilot and the others for the traffic channels), by combining several transmitter ASICs, we can expand the number of channels up to 64. The ASICs are now under use for implementing a line-of-sight (LOS) radio equipment.

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A 1.1V 12b 100MS/s 0.43㎟ ADC based on a low-voltage gain-boosting amplifier in a 45nm CMOS technology (45nm CMOS 공정기술에 최적화된 저전압용 이득-부스팅 증폭기 기반의 1.1V 12b 100MS/s 0.43㎟ ADC)

  • An, Tai-Ji;Park, Jun-Sang;Roh, Ji-Hyun;Lee, Mun-Kyo;Nah, Sun-Phil;Lee, Seung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.122-130
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    • 2013
  • This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

A 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting applications (DMB 응용을 위한 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D 변환기)

  • Cho, Young-Jae;Kim, Yong-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.11 s.353
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    • pp.37-47
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    • 2006
  • This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

SNR and ADC Value Change before and after the injection of contrast medium during DWI test on metastatic spinal cancer patients (전이성 척추암 환자의 확산강조영상 검사 시 조영제 주입 전.후 ADC값의 변화에 대한 고찰)

  • Kim, Eng-Chan;Kim, Ki-Hong;Park, Cheol-Soo;Lee, Sun-Yeob;Yoo, Heung-Joon;Cho, Jae-Hwan;Jang, Hyun-Cheol;Kim, Bo-Hui;Han, Man-Seok
    • Journal of the Korean Society of Radiology
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    • v.5 no.1
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    • pp.37-49
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    • 2011
  • To examine the possible changes in the SNRs, CNRs, and ADC values for lumbar spines with metastasis based on the DW images before and after contrast agent injection taken from metastatic spinal cancer patients using a 1.5 T MR machine. The quantitative analysis revealed that in case of spinal cancer subjects, both SNRs and CNRs at all of those assessed locations significantly increased on the DWI after contrast agent injection compared to before, while on the ADC map images, SNRs significantly decreased. On the other hand, significantly decreased ADC values at all the assessed locations were found on the ADC map images. With reference to the normal group, significantly increased SNRs were found at all of the assessed locations on the DWI image after injection compared to before, while significantly decreased SNRs were found on the ADC map images. Also, significantly decreased ADC values at all the assessed locations were found on the ADC map images. For the qualitative analysis, after contrast agent injection, significantly increased signal intensities were found at the locations with spinal cancer on the DWI. In contrast, significantly decreased signal intensities were found on the ADC map images. The implication from the results showing that SNR and CNR significantly increased while ADC value significantly decreased at, above, and below the location of metastatic spinal cancer on DWI after contrast agent injection is that DWI obtained after contrast agent injection can be made available for wider application to vertebral disorders.

Real-time Nutrient Monitoring of Hydroponic Solutions Using an Ion-selective Electrode-based Embedded System (ISE 기반의 임베디드 시스템을 이용한 실시간 수경재배 양액 모니터링)

  • Han, Hee-Jo;Kim, Hak-Jin;Jung, Dae-Hyun;Cho, Woo-Jae;Cho, Yeong-Yeol;Lee, Gong-In
    • Journal of Bio-Environment Control
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    • v.29 no.2
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    • pp.141-152
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    • 2020
  • The rapid on-site measurement of hydroponic nutrients allows for the more efficient use of crop fertilizers. This paper reports on the development of an embedded on-site system consisting of multiple ion-selective electrodes (ISEs) for the real-time measurement of the concentrations of macronutrients in hydroponic solutions. The system included a combination of PVC ISEs for the detection of NO3, K, and Ca ions, a cobalt-electrode for the detection of H2PO4, a double-junction reference electrode, a solution container, and a sampling system consisting of pumps and valves. An Arduino Due board was used to collect data and to control the volume of the sample. Prior to the measurement of each sample, a two-point normalization method was employed to adjust the sensitivity followed by an offset to minimize potential drift that might occur during continuous measurement. The predictive capabilities of the NO3 and K ISEs based on PVC membranes were satisfactory, producing results that were in close agreement with the results of standard analyzers (R2 = 0.99). Though the Ca ISE fabricated with Ca ionophore II underestimated the Ca concentration by an average of 55%, the strong linear relationship (R2 > 0.84) makes it possible for the embedded system to be used in hydroponic NO3, K, and Ca sensing. The cobalt-rod-based phosphate electrodes exhibited a relatively high error of 24.7±9.26% in the phosphate concentration range of 45 to 155 mg/L compared to standard methods due to inconsistent signal readings between replicates, illustrating the need for further research on the signal conditioning of cobalt electrodes to improve their predictive ability in hydroponic P sensing.

A 10b 50MS/s Low-Power Skinny-Type 0.13um CMOS ADC for CIS Applications (CIS 응용을 위해 제한된 폭을 가지는 10비트 50MS/s 저 전력 0.13um CMOS ADC)

  • Song, Jung-Eun;Hwang, Dong-Hyun;Hwang, Won-Seok;Kim, Kwang-Soo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.5
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    • pp.25-33
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    • 2011
  • This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

Dosimetric Characterization of an Ion Chamber Matrix for Intensity Modulated Radiation Therapy Quality Assurance (세기변조방사선치료 선량분포 확인을 위한 2차원적 이온전리함 배열의 특성분석)

  • Lee, Jeong-Woo;Hong, Se-Mie;Kim, Yon-Lae;Choi, Kyoung-Sik;Jung, Jin-Beom;Lee, Doo-Hyun;Suh, Tae-Suk
    • Progress in Medical Physics
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    • v.17 no.3
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    • pp.131-135
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    • 2006
  • A commercial ion chamber matrix was examined the characteristics and its performance for radiotherapy qualify assurance. The device was the I'mRT 2D-MatriXX (Scanditronix-Wellhofer, Schwarzenbruck, Germany). The 2D-MatriXX device consists of a 1020 vented ion chamber array, arranged in $24{\times}24cm^2$ matrix. Each ion chamber has a volume of $0.08cm^3$, spacing of 0.762 cm and minimum sampling time of 20 ms. For the investigation of the characteristics, dose linearity, output factor, short-term reproducibility and dose rate dependency were tested. In the testing of dose linearity. It has shown a good signal linearity within 1% in the range of $1{\sim}800$cGy. Dose rate dependency was found to be lower than 0.4% (Range: 100-600 Mu/min) relative to a dose rate of 300 Mu/min as a reference. Output factors matched very well within 0.5% compared with commissioned beam data using a ionization chamber (CC01, Scanditronix-Wellhofer, Schwarzenbruck, Germany) in the range of field sizes $3{\times}3{\sim}24{\times}24cm^2$. Short-term reproducibility (6 times with a interval of 15 minute) was also shown a good agreement within 0.5%, when the temperature and the pressure were corrected by each time of measurement. in addition, we compared enhanced dynamic wedge (EDW, Varian, Palo Alto, USA) profiles from calculated values in the radiation planning system with those from measurements of the MatriXX. Furthermore, anon-uniform IMRT dose fluence was tested. All the comparison studies have shown good agreements. In this study, the MatriXX was evaluated as a reliable dosimeter, and it could be used as a simplistic and convenient tool for radiotherapy qualify assurance.

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${T_2}weighted$- Half courier Echo Planar Imaging

  • 김치영;김휴정;안창범
    • Investigative Magnetic Resonance Imaging
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    • v.5 no.1
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    • pp.57-65
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    • 2001
  • Purpose : $T_2$-weighted half courier Echo Planar Imaging (T2HEPI) method is proposed to reduce measurement time of existing EPI by a factor of 2. In addition, high $T_2$ contrast is obtained for clinical applications. High resolution single-shot EPI images with $T_2$ contrast are obtained with $128{\times}128$ matrix size by the proposed method. Materials and methods : In order to reduce measurement time in EPI, half courier space is measured, and rest of half courier data is obtained by conjugate symmetric filling. Thus high resolution single shot EPI image with $128{\times}128$ matrix size is obtained with 64 echoes. By the arrangement of phase encoding gradients, high $T_2$ weighted images are obtained. The acquired data in k-space are shifted if there exists residual gradient field due to eddy current along phase encoding gradient, which results in a serious problem in the reconstructed image. The residual field is estimated by the correlation coefficient between the echo signal for dc and the corresponding reference data acquired during the pre-scan. Once the residual gradient field is properly estimated, it can be removed by the adjustment of initial phase encoding gradient field between $70^{\circ}$ and $180^{\circ}$ rf pulses. Results : The suggested T2EPl is implemented in a 1.0 Tela whole body MRI system. Experiments are done with the effective echo times of 72ms and 96ms with single shot acquisitions. High resolution($128{\times}128$) volunteer head images with high $T_2$ contrast are obtained in a single scan by the proposed method. Conclusion : Using the half courier technique, higher resolution EPI images are obtained with matrix size of $128{\times}128$ in a single scan. Furthermore $T_2$ contrast is controlled by the effective echo time. Since the suggested method can be implemented by software alone (pulse sequence and corresponding tuning and reconstruction algorithms) without addition of special hardware, it can be widely used in existing MRI systems.

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Relationship between Movements of the Foot and Electromyographic Activities of Lower Leg Muscles in Young Women (젊은 여성의 발동작과 몇몇 하퇴근 근전도와의 관계)

  • Choe, Myoung-Ae;Shin, Dong-Hoon
    • The Korean Journal of Physiology
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    • v.18 no.1
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    • pp.81-96
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    • 1984
  • As the crippled persons work mostly in a sitting position and would be engaged in a foot-pressing job, it is necessary to assess their degree of participation of important muscles in various modes of foot activities. In this regard, it deems to be urgent to establish the reference standards for healthy persons. The present study has been undertaken to determine the degree of participation of the M. tibialis anterior, M. gastrocnemius and M. soleus in heel pressing, foot-flat pressing and forefoot pressing motion under varying forces, and in order to compare the electrical activities of three muscles with each other, and to analyse the time sequence between force and appearance or disappearance of EMG recording. Sixty-three healthy young women ranging from age of 18 to 23 were examined. The results obtained were as follows: 1. Participation of three muscles in foot movement under varying forces: A) Both gastrocnemius muscles or left soleus muscle did not contribute to heel pressing motion. Activity of both tibialis anterior muscles was the greatest among three muscles at heel pressing motion and the degree of their activities was proportional to force. B) Activities of left tibialis anterior muscle and both gastrocnemius muscles were negligible under 3 kg force at foot-flat pressing movement. Left gastrocnemius muscle did not contribute to foot-flat pressing under 6 or 9 kg force. Although activities of both soleus muscles and both tibialis anterior muscles were small, the degree of their activities increased with force at foot-flat pressing movement. C) Activities of both tibialis anterior muscles were negligible under 3 kg force at forefoot pressing motion. Activity of both soleus muscles was the greatest among 3 muscles and the degree of their activities increased with force at forefoot pressing motion. Both tibialis anterior muscles participated in forefoot pressing motion with severe exertion. 2. Electrical activities by foot movement under varying forces : A) Electrical activities were prominent in both tibialis anterior muscles and the level of their activities was linear with force at heel pressing motion. The degree of participation of both soleus muscles was small at heel pressing motion. B) Electrical activity of tibialis anterior muscle was the greatest among 3 muscles at foot-flat pressing movement and was followed by that of soleus muscle. Level of electrical activities increased with force in left soleus muscle and right tibialis anterior muscle at foot-flat pressing movement. C) Electrical activity of both soleua muscles was the greatest among 3 muscles at forefoot pressing movement and that of tibialis anterior muscle was next to soleus muscle. Level of electrical activities was proportional to force in left tibialis anterior muscle, right gastrocnemius muscle and both soleus muscles at forefoot pressing movement. 3. Time between starting signal and initiation of contraction of heel pressing and forefoot pressing motion in 3 muscles was longer than that of foot-flat pressing movement. Time of relaxation in 3 muscles was longer than that of contraction under varying forces. EMG recording appeared before initiation of contraction in both tibialis anterior muscles at heel pressing motion and in both soleus muscles at forefoot pressing movement under varying forces. Time of initiation of contraction was similar in both sides of tibialis anterior muscles under varying forces and time of onset of contraction at foot-flat pressing motion was the shortest. 4. Forefoot pressing movement would be encouraged in paralysis of tibialis anterior muscle, while heel pressing motion would be encouraged in paralysis of triceps surae muscle.

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