• Proceedings of the IEEK Conference
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• 2000.11c
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• pp.47-50
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• 2000

Recently many efforts on the development of automatic processing system for delivery sequence sorting have been performed in ETRI , which requires the use of postal 4-state bar code system to encode delivery points. The 4-state bar code called postal 4-state bar code for high speed processing that has been specifically designed for information processing of logistics and automatic processing of the mail items. This paper describes a method of Reed-Solomon encoding for creating error correction codeword of 4-state bar code.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6B
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• pp.984-990
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• 2010

In Current Digital $C^3$ Devices(Communication, Computer, Consumer electronic devices), Reed-Solomon encoder is essentially used. For example we should use RS encoder in DSP LSI of CDMA Mobile and Base station modem, in controller LSI of DVD Recorder and that of computer memory(HDD or SSD memory). In this paper, we propose new economical multiplierless (also without divider) RS encoder design method. The encoder has Arbitrary parity positions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.649-654
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• 2011

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.4
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• pp.544-551
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• 2002

In this paper, BER performance of DS/CDMA-BPSK system is analyzed in mixed lading channel that is consist of Rayleigh fadins Rician fading, and shadowed Rician fading. From the results, we know that proposed mixed fading model is very suitable to describe the different channel situations. and, the occupancy probability and the shadowing depth are very dependent to the system performance. Finally, we know that the Reed-Solomon coded DS/ CDMA-BPSK system is very robust to simultaneous user interference and mixed lading channel.

• ETRI Journal
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• v.25 no.5
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• pp.305-314
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• 2003

In this paper, we present a soft IP compiler for the Reed-Solomon decoder that generates a fully synthesizable VHDL core exploiting characteristic parameters and design constraints that we newly classify for the soft IP. It produces a structural design with an estimable regular architecture based on a finite state machine with a datapath (FSMD). Since characteristic parameters provide different design points on the design space, using one of two simple procedures called the constructive search with area increment (CSAI) and constructive search with speed decrement (CSSD) for design space exploration, the core compiler makes it possible for an IP user to create the Reed-Solomon decoder with appropriate sub-architectures without synthesizing many models. Experimental results show that the IP compiler can apply to several industry standards.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1C
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• pp.8-13
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• 2011

In this paper, we show new method to find error locations of 2 eight bit symbol errors for 2 error correcting Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by partitioning the 8 bit operations into 4 bit arithgmatic and logic operations. This Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.281-284
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• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk with double error detecting and correcting capability. A variety of error correction codes(ECCs) have been used in magnetic recordings, and optical recordings. Among the various types of ECCs, Reed Solomon(RS) codes has emerged as one the most important ones. The most complex circuit in the RS decoder is the part for finding the error location numbers by solving error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid's algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and peformed logic synthesis using the SYNOPSYS CAD tool. The total umber of gate is about 11,000 gates.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.7
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• pp.909-915
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• 1999

In this paper, we propose an efficient VLSI architecture of Reed-Solomon(RS) decoder. To improve the speed. we develope an architecture featuring parallel and pipelined processing. To implement the parallel and pipelined processing architecture, we analyze the RS decoding algorithm and the honor's algorithm for parallel processing and we also modified the Euclid's algorithm to apply the efficient parallel structure in RS decoder. To show the proposed architecture, the performance of the proposed RS decoder is compared to Shao's and we obtain the 10 % efficiency in area and three times faster in speed when it's compared to Shao's time domain decoder. In addition, we implemented the proposed RS decoder with Altera FPGA Flex10K-50.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.306-312
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• 2000

In this paper, the efficient architecture of small Reed-solomon architecture is suggested. Here, 3-stage pipeline is adopted. In decoding, error-location polynomials are obtained by BMA using fast iteration method, and syndrome polynomials, where calculation complexity is required, are obtained by parallel calculation using ROM table, and the roots of error location polynomial are calculated by ROM table using Chein search algorithm. In the suggested decoder, it is confirmed that 3 symbol random errors can be corrected and 124Mbps decoding rate is obtained using 25 Mhz system clock.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.3
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• pp.147-152
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• 1985

The error-trapping decoder is constructed for the (7, 3) Reed-Solomon code. The syndrome resister is constructed with the encoder and the substanial test logic circuits. The element of GF(8) is represented by the triple D-flip-floops. The hardware is constructed. And it is controlled by the micro computer(Apple II). The time for the encoding and the decoding were $350\musecs and 910u secs respectively. The experimental results show that the two symbol errors were corrected and 4-bit-binary-burst errors were also corrected.