• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.907-910
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• 2009

This paper is the FPGA Implementation of Reed-Solomon Encoder that is one of Error control Codes. Reed-Solomon codes are block-based error control codes with a wide range of applications in digital communications. RS codes are strong on burst errors because it process signals as symbol. We simulate this system using Matlab from Mathworks and design it using System Generator from Xilinx. We refer Matlab source in Implementation of Reed-Solomon Error Control Coding for Compressed Images by Simon Anthony Raspa.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.11
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• pp.13-20
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• 2005

For Modern Consumer and Communication Elecronic Devices, Always Error Protecting HW and SW is used. The Core is RS(Reed Solomon) Codec in Galois Field GF($2^8$). Here New 2 to 3 Symbol RS Decoder Design and Encoder design Method using Normalized error position Value is described. Examples are given to show the methods are working well.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.285-288
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• 2000

In this paper, we propose a Reed-Solomon decoder for the DVD Reed-Solomon(RS) product code based on new efficient euclid cell architecture suitable for Modified Euclid Algorithm. We synthesized the RS decoder using Hyundai 0.65um CMOS standard cell library and compared the performance of the decoder with one of the conventional architectures. The result shows that the proposed euclid cell use about 32% less symbol time.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.7
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• pp.909-915
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• 1999

In this paper, we propose an efficient VLSI architecture of Reed-Solomon(RS) decoder. To improve the speed. we develope an architecture featuring parallel and pipelined processing. To implement the parallel and pipelined processing architecture, we analyze the RS decoding algorithm and the honor's algorithm for parallel processing and we also modified the Euclid's algorithm to apply the efficient parallel structure in RS decoder. To show the proposed architecture, the performance of the proposed RS decoder is compared to Shao's and we obtain the 10 % efficiency in area and three times faster in speed when it's compared to Shao's time domain decoder. In addition, we implemented the proposed RS decoder with Altera FPGA Flex10K-50.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6B
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• pp.984-990
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• 2010

In Current Digital $C^3$ Devices(Communication, Computer, Consumer electronic devices), Reed-Solomon encoder is essentially used. For example we should use RS encoder in DSP LSI of CDMA Mobile and Base station modem, in controller LSI of DVD Recorder and that of computer memory(HDD or SSD memory). In this paper, we propose new economical multiplierless (also without divider) RS encoder design method. The encoder has Arbitrary parity positions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.48-55
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• 2009

This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-${\mu}m$ CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300MHz and has a throughput of 115-Gb/s for 0.13-${\mu}m$ CMOS technology. As a result, the proposed three-parallel RS-FEC architecture has a much higher data processing rate and low hardware complexity compared with the conventional two-parallel, three-parallel and serial RS-FEC architectures.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.10-17
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• 1989

The Berlekamp-Massey algorithm, the method of using the Euclid algorithm, and Fourier transforms over a finite field can be used for the decoding of Reed-Solomon codes (called RS codes). RS codes can also be decoded by the algorithm that was developed by Peterson and refined by the Gorenstein and Zierler. However, the decoding of RS codes using the Peterson-Gorenstein-Zieler algorithm offers sometimes computational or implementation advantages. The decoding procedure of the double-error correcting (31,27) Rs code over the symbol field GF ($2^5$) will be analyized in this paper. The complete analysis, gate array design, and implementation for encoder/decoder pair of (31.27)RS code are performed with a strong theoretical justification.

• Journal of the Semiconductor & Display Technology
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• v.13 no.4
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• pp.7-13
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• 2014

In this paper, an area-efficient degree-computationless modified Euclidean (DCME) algorithm is presented and implemented for high-speed Reed-Solomon (RS) decoder. The DCME algorithm can be used to solve the key equation in Reed-Solomon decoder to get the error location polynomial and the error value polynomial. A pipelined recursive structure is adopted for reducing the area of key equation solver (KES) block with sacrifice of an amount of decoding latency. For comparisons, KES block for RS(255,239,8) decoder with the proposed architecture is implemented using Verilog HDL and synthesized using Synopsys design tool and 65nm CMOS technology. The synthesis results show that the proposed architecture can be implemented with less gate counts than other existing DCME architectures.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.262-265
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• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.8-13
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• 2006

A new RS(Reed Solomon) Decoder design method, using Galois Subfield GF($2^4$) Multiplier, is described. The Decoder is designed using Normalized error position stored ROM. Here New Inverse Calculator in GF($2^8$) is designed, which is simpler and faster than the classical GF($2^8$) direct inverse calculator, using the Galois Subfield GF($2^4$) Arithmatic operator.