• Aerospace Engineering and Technology
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• v.3 no.1
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• pp.179-187
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• 2004

We consider some problems of the Modified SPRT(Sequential Probability Ratio Test) method for fault detection and isolation of inertial redundant sensor systems and propose an Advanced SPRT method which solves the problems of the Modified SPRT method. The problems of the Modified SPRT method to apply to inertial sensor system come from the effect of inertial sensor errors and the correlation of parity vector components. We use a two-stage Kalman filter to remove effects of the inertial sensor errors and propose the modified parity vector and the controlled parity vector which reduces the effect of correlation of parity vector components. The Advanced SPRT method is derived form the modified parity vector and the controlled party vector. Some simulation results are presented to show the usefulness of the Advanced SPRT method to redundant inertial sensor systems.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1889-1896
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• 2011

There has been a lot of researches to develop techniques that provide redundant paths, there by making Multistage Interconnection Networks(MINs) fault tolerant. So far, the redundant paths in MINs have been realized by adding additional hardware such as extra stages or duplicated data links. This paper presents a new MIN topology called Hierarchical MIN. The proposed MIN is constructed with 2.5N-4 switching elements, which are much fewer than that of the classical MINs. Even though there are fewer hardware than the classical MINs, the HMIN possesses the property of full access and also provides alternative paths for the fault tolerant. Furthermore, since there is the short cut in HMIN for the localized communication, it takes advantage of exploiting the locality of reference in multiprocessor systems. Its performance under varying degrees of localized communication is analysed and simulated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• Korean Journal of Computational Design and Engineering
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• v.1 no.1
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• pp.33-44
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• 1996

This study deals with the development of wire path searching module as a part of automobile wire harness design system. Wire path searching module manages the free space, finds transition locations, and creates bundle paths to dramatically reduce a tedious iterative routing process which results in easy optimization of the bundle paths. A prime policy in the system configuration is to compromise between man's and computer's ability, and make it possible a designer's leading role in designing process. Human input is indispensable to cope with the special cases which were not considered in the initial design stage of the system. In this study, we improve the previous shortest-path-finding algorithm, (VGraph and RCA method) into a new method called Extended RCA. Bundles, connectors and transitions are handled as objects so one can manage and modify physical properties of the objects easily. Therefore a verification is allowed at any desired stage of design. The reuse of previous result is facilitated by using Dependency Structure, which represents the mutual relations among connectors, transitions, and bundles. Dependency Structure makes it possible the elimination of redundant calculating process, and consequently shorter routing time.

• Bulletin of the Korean Chemical Society
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• v.30 no.2
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• pp.323-326
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• 2009

SR proteins are essential splicing regulators and also modulate alternative splicing events, which function both as redundant and substrate-specific manner. The Drosophila B52/SRp55, a member of the SR protein family, is essential for the fly development in vivo, as deletion of B52 gene results in lethality of animals at the second instar larval stage. Identification of the splicing target genes of B52 thus should be crucial for the understanding of the specific developmental role of B52 in vivo. In this study, we performed whole-genome DNA microarray experiments with a B52- knock-out animal. Analysis of the microarray data not only provided the B52-dependent gene expression signature, but also revealed a larval-stage specific, alternative splicing target gene of B52. Our result thus provides a starting point to understand the essential function of B52 at the organismal level.

• Journal of Korea Multimedia Society
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• v.24 no.5
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• pp.659-666
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• 2021

With the continuous development of deep learning, human behavior recognition algorithms have achieved good results. However, in a multi-person recognition environment, the complex behavior environment poses a great challenge to the efficiency of recognition. To this end, this paper proposes a multi-person pose estimation model. First of all, the human detectors in the top-down framework mostly use the two-stage target detection model, which runs slow down. The single-stage YOLOv3 target detection model is used to effectively improve the running speed and the generalization of the model. Depth separable convolution, which further improves the speed of target detection and improves the model's ability to extract target proposed regions; Secondly, based on the feature pyramid network combined with context semantic information in the pose estimation model, the OHEM algorithm is used to solve difficult key point detection problems, and the accuracy of multi-person pose estimation is improved; Finally, the Euclidean distance is used to calculate the spatial distance between key points, to determine the similarity of postures in the frame, and to eliminate redundant postures.

• 한국정보통신설비학회:학술대회논문집
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• 2002.08a
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• pp.27-30
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• 2002

10-bit 해상도, 10MS/s의 ADC를 Stage 당 1.5-Bit의 Resolution을 가지는 Redundant signed digit(RSD) 방식의 파이프라인 구조를 이용하여 설계하였다. Error Correction Logic을 사용함으로써 비교기를 Coarse하게 설계하였고 잔류 전압 증폭기의 최적 Scaling을 통하여 일반적인 ADC에 비해 성능 저하 없이 효율적으로 소비 전력을 감소시켰다. 또한, Charge Pump의 선택적 사용을 통해 기생 커패시턴스의 영향을 최소화함으로써 잔류전압 증폭기의 출력 전압 특성을 향상 시켰다. 삼성 0.35u CMOS 공정 파라미터를 이용하여 입력 전압 $-1{\sim}1V$, 공급 전압 $-1.5{\sim}1.5V$에서 18.73mW로 설계하였으며 HSPICE로 시뮬레이션 하였다.

• Proceedings of the IEEK Conference
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• summer
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• pp.61-65
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• 2004

An on-chip debugging unit is proposed aiming performance enhancement of JTAG-based SoC systems. The proposed unit comprises a JTAG module and a core breaker. The IEEE 1149.1 standard has been modified and applied to the new JTAG module. The proposed unit eliminates redundant clock cycles included in the TAP command execution stage reducing overall debugging time. TAP execution commands are repeatedly issued to perform debugging of complicated SoC systems. Simulation on the proposed unit shows some $14\%$ performance enhancement and $50\%$ gate count reduction compared to the conventional ones.

• International Journal of Contents
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• v.14 no.4
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• pp.24-29
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• 2018

EEG-based brain-computer interfaces has focused on explicitly expressed intentions to assist physically impaired patients. For EEG-based-computer interfaces to function effectively, it should be able to understand users' implicit information. Since it is hard to gather EEG signals of human brains, we do not have enough training data which are essential for proper classification performance of implicit intention. In this paper, we improve the subject independent classification of implicit intention through the generation of additional training data. In the first stage, we perform the PCA (principal component analysis) of training data in a bid to remove redundant components in the components within the input data. After the dimension reduction by PCA, we train ICA (independent component analysis) network whose outputs are statistically independent. We can get additional training data by adding Gaussian noises to ICA outputs and projecting them to input data domain. Through simulations with EEG data provided by CNSL, KAIST, we improve the classification performance from 65.05% to 66.69% with Gamma components. The proposed sample generation method can be applied to any machine learning problem with fewer samples.

• Journal of Multimedia Information System
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• v.6 no.1
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• pp.7-14
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• 2019

This work presents a virtual prototyping design approach for an area-based image stitching hardware. The virtual hardware obtained from virtual prototyping is equivalent to the conceptual algorithm, yet the conceptual blocks are linked to the actual circuit components including the memory, logic gates, and arithmetic units. Through the proposed method, the overall structure, size, and computation speed of the actual hardware can be estimated in the early design stage. As a result, the optimized virtual hardware facilitates the hardware implementation by eliminating trail design and redundant simulation steps to optimize the hardware performance. In order to verify the feasibility of the proposed method, the virtual hardware of an image stitching platform has been realized, where it required 10,522,368 clock cycles to stitch two $1280{\times}1024$ sized images. Furthermore, with a clock frequency of 250MHz, the estimated computation time of the proposed virtual hardware is 0.877sec, which is 10x faster than the software-based image stitch platform using MATLAB.