• Journal of KIISE:Information Networking
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• v.34 no.3
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• pp.193-202
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• 2007

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches under Hot-spot environment is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch. The performance of the multiple-buffered $a{\times}a$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• Journal of Power Electronics
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• v.14 no.3
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• pp.507-518
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• 2014

This paper presents a new cascaded asymmetrical single phase multilevel converter with a lower number of power semiconductor switches and isolated DC sources. Therefore, the number of power electronic devices, converter losses, size, and cost are reduced. The proposed multilevel converter topology consists of two H-bridges connected in cascaded configuration. One H-bridge operates at a high frequency (high frequency inverter) and is capable of developing a two level output while the other H-bridge operates at the fundamental frequency (low frequency inverter) and is capable of developing a multilevel output. The addition of each power electronic switch to the low frequency inverter increases the number of levels by four. This paper also introduces a hybrid switching algorithm which uses very simple arithmetic and logical operations. The simplified hybrid switching algorithm is generalized for any number of levels. The proposed simplified switching algorithm is developed using a TMS320F2812 DSP board. The operation and performance of the proposed multilevel converter are verified by simulations using MATLAB/SIMULINK and experimental results.

• Journal of IKEEE
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• v.23 no.1
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• pp.53-57
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• 2019

In this paper, we propose a new Z-source inverter structure to reduce switching elements and PWM pulse control method. Z-network is connected between the inverter backplane and ground, rather than between the DC voltage and the inverter in an improved Z-source inverter. And the improved Z-source inverter has the advantages of limiting the capacitor inrush current and reducing the capacitor voltage stress. We have proposed a topology of a new type of switch-reduced improved Z-source inverter that reduces the number of switches from six to four in an improved Z-source inverter and developed a PWM control method suitable for the proposed topology. The characteristics and the performance of the proposed method were verified by using PSIM simulation.

• Journal of Power Electronics
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• v.18 no.3
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• pp.672-680
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• 2018

A bidirectional exponential-gain switched-capacitor (SC) DC-DC converter is developed in this paper. When compared with existing exponential SC converters, the number of switches is significantly reduced and its structure is simplified. The voltage transfer features, voltage ripple across capacitors, efficiency and output impedance of the proposed converter are analyzed in detail. Optimization of the output impedance is also discussed and the best type of capacitance distribution is determined. A common function of the voltage gain to the output impedance is found among the proposed converter and other popular SC voltage multipliers. Experimental evaluation is carried out with a 6-24V bidirectional prototype converter.

• Journal of Electrical Engineering and Technology
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• v.8 no.5
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• pp.1138-1145
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• 2013

A novel predictive current control strategy for a sparse matrix converter is presented. The sparse matrix converter is functionally-equivalent to the direct matrix converter but has a reduced number of switches. The predictive current control uses a model of the system to predict the future value of the load current and generates the reference voltage vector that minimizes a given cost function so that space vector modulation is achieved. The results show that the proposed controller for sparse matrix converters controls the load current very effectively and performs very well through simulation and experimental results.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.481-482
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• 2007

This paper describes the design of a l0-bit 100 KSample/S CMOS A/D Converter for biomedical applications such as pulse oximetry, body weight scale, ECG etc. We adopted an asynchronous architecture in the 10-b DAC design and hence reduces the number of switches by 11 and resistors by 64 compared with the conventional l0-b DAC. We also reduced the power consumption compare with the conventional architecture by 0.4mW. Output offset cancellation technique is applied to the design of comparator. The total power consumption of designed circuit is 190uW at the supply voltage of 1.8V with the 0.18um general CMOS technology.

• Journal of Power Electronics
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• v.11 no.5
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• pp.655-661
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• 2011

This paper presents two topologies for single-stage single-phase double-buck type PFC converters, designed to operate at high power factor, near sinusoidal input currents and adjustable output voltage. Unlike the known buck type PFC topologies, in which the output voltage is always lower than the maximum input voltage, the proposed converters can operate at output voltages higher than the ac input peak voltage. A reduced number of switches on the main path of the current are another characteristic of the two proposed topologies. To shape the input line currents, a fast and robust controller based on a sliding mode approach is proposed. This active non-linear control strategy, applied to these converters allows high quality input currents. A Proportional Integral (PI) controller is adopted to regulate the output voltage of the converters. This external voltage controller modulates the amplitude of the sinusoidal input current references. The performances of the presented rectifiers are verified with experimental results.

• Proceedings of the KIEE Conference
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• 2007.04c
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• pp.100-102
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• 2007

In this paper, a modified multi-level convert for low cost high speed switched reluctance (SR) drive is proposed The proposed multi-level converter has reduced number of power switches and diodes than that of a conventional asymmetric converter for SRM, and lower voltage rating of the dump capacitor comparing with energy efficient c-dump converter. It can supply five operating modes that is boosted, DC-link, zero, negative bias and negative boosted voltage. The proposed multi-level converter has fast excitation and demagnetization modes of phase current, so dynamic response can be achieved. The proposed multi-level converter is verified by computer simulation and experimental results.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.653-656
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• 2005

New charge-recycling structure and driving scheme for TFT-LCD source-driver IC application are proposed. The number of additional switches for the charge recycling is greatly reduced. An experimental prototype 6-bit source driver with five-level seven-phase charge recycling implemented in a $0.35-{\mu}m$ CMOS technology demonstrates that the quiescent current is only 3.1 mA, dynamic power saving is 75 %, and the settling time, which includes the charge-recycling and data driving, is within 25 $25{\mu}s$.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.512-514
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• 2007

The number of transformers and the size of transformers in inverter using 3-phase transformer could be reduced compare with a multi-level inverter using single phase transformer. but still the 3-phase transformer inverter needs many switches. In this study, we proposed the isolated multi-level inverter using 3-phase transformers and common arm. Also, the equal-area method is used to calculate conduction angle with switching frequency equal to output fundamental frequency and it can reduce harmonics component of output voltage and switching loss. Finally, We tested multi-level inverter to clarify electric circuit and reasonableness through Matlab simulation and experiment by using prototype inverter.