• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.9
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• pp.472-477
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• 2006

This paper presents a new voltage/current mixed method for driving synchronous rectifiers (SR) adapted to the flyback topology. The synchronous rectifier driven by the proposed voltage/current mixed method can operate at a wide load range with high efficiency. The gate voltage of MOSFET in the synchronous rectifier can be easily controlled by changing the ratio of resistors, irrespective of a line and load fluctuation. A 200W (12V/17A) prototype converter was built and an efficiency of 93% was measured at 10A load current.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.22-25
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• 2007

The paper describes a power factor correction high efficiency PWM single-phase rectifier. Its good characteristics such as simple circuit structure, simple PWM control, low switch stress, and low VAR rating of commutation circuits make the proposed rectifier very suitable for various unidirectional power applications. In particular, the design guide line is suggested to make the circuit design of the proposed rectifier easy and fast.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1226-1235
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• 2016

For wearable health monitoring systems, a fundamental problem is the limited space for storing energy, which can be translated into a short operational life. In this paper, a highly efficient active voltage doubling rectifier with a wide input range for micro-piezoelectric energy harvesting systems is proposed. To obtain a higher output voltage, the Dickson charge pump topology is chosen in this design. By replacing the passive diodes with unbalanced-biased comparator-controlled active counterparts, the proposed rectifier minimizes the voltage losses along the conduction path and solves the reverse leakage problem caused by conventional comparator-controlled active diodes. To improve the rectifier input voltage sensitivity and decrease the minimum operational input voltage, two low power common-gate comparators are introduced in the proposed design. To keep the comparator from oscillating, a positive feedback loop formed by the capacitor C is added to it. Based on the SMIC 0.18-μm standard CMOS process, the proposed rectifier is simulated and implemented. The area of the whole chip is 0.91×0.97 mm², while the rectifier core occupies only 13% of this area. The measured results show that the proposed rectifier can operate properly with input amplitudes ranging from 0.2 to 1.0V and with frequencies ranging from 20 to 3000 Hz. The proposed rectifier can achieve a 92.5% power conversion efficiency (PCE) with input amplitudes equal to 0.6 V at 200 Hz. The voltage conversion efficiency (VCE) is around 93% for input amplitudes greater than 0.3 V and load resistances larger than 20kΩ.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.6
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• pp.406-410
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• 2019

Three-level (3L) DC-DC converters are appropriate for high-input-voltage applications. Although the voltage stress of TL converter switches can be reduced to half of the input voltage, the primary side has a large circulating current, which degrades efficiency. In this study, a dual half-bridge cascaded TL converter is presented to reduce this circulating current and thus decrease the conduction loss of the primary circuit. Moreover, the proposed converter can reduce the voltage stress of rectifier diodes, thereby reducing their conduction loss. Therefore, efficiency can be improved by reducing the conduction loss of the primary circuit and rectifier diodes.

• Journal of Advanced Marine Engineering and Technology
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• v.29 no.2
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• pp.243-250
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• 2005

A new technique for improving the efficiency of single-Phase high-frequency switch-mode boost rectifiers is proposed. This rectifier includes an additional boost converter that parallels the main high-frequency switching device. The additional converter. which is controlled at lower frequencies. bypasses most of the current in the main switch and the high frequency switching loss is greatly reduced accordingly. The rectifier works cooperatively in high efficiency and as if it were a conventional rectifier with one switching device. The proposed scheme is verified by computer simulation using software PSIM.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.341-345
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• 2004

A high efficiency and low device stress voltage and current clamping BVS PWM asymmetrical half bridge converter is proposed in this paper. To achieve the ZVS of power switches along the wide load range, the transformer leakage inductor $L_{Ikg}$ is increased. Then, to solve the problem related to ringing in the secondary rectifier caused by the resonance between $L_{Ikg}$ and rectifier junction capacitors, the proposed converter employs a voltage and current clamping cell, which helps voltages and currents of rectifier diodes to be clamped at the output voltage and output current, respectively. Therefore, no RC-snubber for rectifier diodes is needed and a high efficiency as well as low noise output voltage can be realized. In addition, since all energy stored in $L_{Ikg}$ is transferred to the output side, the circulating energy problem can be effectively solved and duty loss does net exist. The operational principle, theoretical analysis, and design considerations are presented. To confirm the operation, validity, and features of the proposed circuit, experimental results from a 425W, 385-170Vdc prototype are presented.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.56-62
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• 2013

We present a rectifier for wireless power transmission using multiplier configuration in layout for MOSFETs which works at 13.56 MHz, designed to fit in CMOS process where conventionally used diodes are replaced with the cross-coupled MOSFETs. Full bridge rectifier structure without comparators is employed to reduce current consumption and to be working up to higher frequency. Multiplier configuration designed in layout reduces time delay originated from parasitic series resistance and shunt capacitance at each finger due to long connecting layout, leading to fast transition from on-state to off-state cross-coupled circuit structure and vice versa. The power conversion efficiency is significantly increased due to this fast transition time. The rectifier is fabricated in $0.11{\mu}m$ CMOS process, RF to DC power conversion efficiency is measured as 86.4% at the peak, and this good efficiency is maintained up to 600 MHz, which is, to our best knowledge, the highest frequency based on cross-coupled configuration.

• Journal of Power Electronics
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• v.14 no.5
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• pp.815-826
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• 2014

An improved bridgeless interleaved boost power factor correction (PFC) rectifier to improve power efficiency and component utilization is proposed in this study. With combined conventional bridgeless PFC circuit and interleaved technology, the proposed rectifier consists of two interleaved and magnetic inter-coupling boost bridgeless converter cells. Each cell operates alternatively in the critical conduction mode, which can achieve the soft-switching characteristics of the switches and increase power capacity. Auxiliary blocking diodes are employed to eliminate undesired circulating loops and reduce current-sensing noise, which are among the serious drawbacks of a dual-boost PFC rectifier. Magnetic component utilization is improved by symmetrically coupling two inductors on a unique core, which can achieve independence from each other based on the auxiliary diodes. Through the interleaved approach, each switch can operate in the whole line cycle. A simple control scheme is employed in the circuit by using a conventional interleaved controller. The operation principle and theoretical analysis of the converter are presented. A 600 W experimental prototype is built to verify the theoretical analysis and feasibility of the proposed rectifier. System efficiency reaches 97.3% with low total harmonic distortion at full load.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.34-42
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• 2012

In this paper, a wide-input range CMOS multi-mode rectifier for wireless power transfer system is presented. The output voltage of multi-mode rectifier is sensed by comparator and switches are controlled based on it. The mode of multi-mode rectifier is automatically selected by the switches among full-wave rectifier, 1-stage voltage multiplier and 2-stage voltage multiplier. In full-wave rectifier mode, the rectified output DC voltage ranges from 9 V to 19 V for a input AC voltage from 10 V to 20 V. However, the input-range of the multi-mode rectifier is more improved than that of the conventional full-wave rectifier by 5V, so the rectified output DC voltage ranges from 7.5 V to 19 V for a input AC voltage from 5 V to 20 V. The power conversion efficiency of the multi-mode rectifier is 94 % in full-wave rectifier mode. The proposed multi-mode rectifier is fabricated in a $0.35{\mu}m$ CMOS process with an active area of $2500{\mu}m{\times}1750{\mu}m$.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.299-304
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• 2000

In this paper we investigate accurately the input-output characteristic of single-phase diode rectifier. The diode rectifier has some advantages of simplicity cost and high-efficiency. But it has some defects which THD of input current low PF and voltage drop of output side. In order to compensate it we analyzed using the parameter variation and introduced capacitor insertion method for reducing the distortion and increasing the PF.