• 한국CDE학회논문집
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• 제22권2호
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• pp.129-140
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• 2017

This paper presents a systematic approach for design of timely and proper layouts of a manufacturing system facilitating reconfigurability, referred to as a reconfigurable manufacturing system. A proper methodology for design of a system layout is required for reconfiguration planning - adding or removing machines for supplying the exact capacity needed to fulfill market demands, as well as minimizing the cost of adding new machines. In this paper, theory of constraints is used to make reconfiguration manufacturing systems more cost-effective and efficiency. The proposed approach is validated by using a real industrial case. This paper suggests that the proposed study should be performed concurrently with the design of a new manufacturing system.

• 한국전자파학회논문지
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• 제21권4호
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• pp.381-391
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• 2010

본 논문에서는 상용 초고주파 MEMS 스위치를 이용하여 세 개의 주파수 대역에서 재구성 동작이 가능한 주파수 재구성 능동 배열 안테나 시스템(Reconfigurable Active Array Antenna System: RAA System)을 제안하였다. MEMS 스위치는 삽입 손실 및 선형성 특성이 우수하고 격리도가 높아 주파수 재구성 시스템 구현 시, 재구성을 위한 스위치로 인한 성능 열화가 거의 없다는 장점이 있다. 제안된 주파수 재구성 능동 배열 안테나 시스템은 간단한 구조의 임피던스 매칭 회로(Reconfigurable impedance Matching Circuit: RMC)를 갖는 주파수 재구성 증폭기(Reconfigurable Front-end Amplifier: RFA)가 집적화 되어 있으며, 안테나 방사체(Reconfigurable Antenna Element: RAE)와 재구성 제어 보드(Reconfiguration Control Board: RCB)로 구성되어 있다. 본 논문에서 제안한 RAA 시스템은 850 MHz, 1.9 GHz, 3.4 GHz의 세 개 주파수로 재구성되어 동작하며, 안테나 방사체는 $2{\times}2$ 배열을 가지고 각각의 방사체는 광대역 다이폴 형태를 갖는다. 제작된 RAA 시스템은 실험을 통하여 그 타당성을 확인하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.174-181
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• 2004

In this paper, we review the four receiver architectures and four methods for multi-standard receiver design. Propose reconfigurable RF block can be used for both low-IF and direct conversion architecture. Also, using reconfigurable mixer method, it can be operated at $2{\sim}6$ GHz range for multi-standard receiver. It consists of wideband mixer, filter, and automatic gain control amplifier and to get wide-band operation, $2{\sim}6$ GHz, wide-band mixer use flexible input matching method. Besides, to design multi-standard receiver, LNA bank that support each standard is necessary and it has good performance to compensate the performance of wide-band mixer. Finally, we design and simulate proposed reconfigurable RF block and to prove that it has acceptable performances for various wireless standards, the LNA bank that supports both IEEE 802.11a/b/g and WCDMA is also designed and simulated with it.

• 인터넷정보학회논문지
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• 제7권2호
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• pp.121-136
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• 2006

재구성(reconfiguration) 기능을 갖춘 SDR(Software Defined Radio) 시스템이 가져야할 소프트웨어 아키텍처와 컴포넌트들 사이에 필요한 프로토콜에 대한 분석을 수행하고 기능 구현을 위한 시스템 설계 내용을 제시한다. 이를 위해 SDR의 기술동향을 분석하고, SDR 시스템을 구축하기 위한 모델을 임베디드 시스템 (Imbedded System)에 입각하여 설계하였다. SDR 시스템 아키텍처는 하드웨어, 운영체제, 미들웨어, 서비스 객체, 응용 계층으로 이루어지는 5계층 구조를 제시한다. SDR 시스템은 리눅스 운영체제 기반에서 구축하였으며, SDR의 주요 특징인 확장성 (scalability)과 재구성 기능이 상호보완적이 되도록 하였다. 5계층 구조에서 SDR의 핵심 기능인 소프트웨어 다운로드 (Software Download) 기능을 구현하기 위한 프로토콜 및 객체의 상태천이도를 수용하는 소프트웨어 설계 내용을 제시한다.

• 제어로봇시스템학회논문지
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• 제9권2호
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• pp.99-106
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• 2003

A new reconfigurable model following flight control method based on direct adaptive scheme is presented. Using the timescale separation principle, both the inner-loop and the outer-loop states are controlled simultaneously. For the timescale separation assumption to be satisfied, the inner-loop model dynamics is set to be fast whereas the outer-loop model dynamics is set to be relatively slow. The stability and convergence of the proposed control law is proved by Lyapunov theorem. One of the merits of the proposed reconfigurable controller is that the FDI process and the persistent input excitation are not necessary, which is suitable for the flight control system. To evaluate the reconfiguration performance of the proposed control method, numerical simulation is performed using six degree-of-freedom nonlinear dynamics.

• 전기전자학회논문지
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• 제24권1호
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• pp.186-193
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• 2020

본 논문에서는 Zynq SoC 환경에서 재구성 가능한 하드웨어 가속기를 지원하는 멀티쓰레딩 시스템을 제안한다. 압축된 정지 영상의 픽셀 데이터를 복원하는 고성능 JPEG 디코더를 구현하고 2D-IDCT 함수를 재구성 가능한 하드웨어 가속기로 설계하여 성능을 검증한다. 구현된 시스템에서 최대 4개의 재구성 가능한 하드웨어 가속기는 소프트웨어 쓰레드와 동기화되어 연산을 수행할 수 있으며 이미지 해상도와 압축률에 따라 다른 성능 향상을 보인다. 1080p 해상도 영상의 경우 17:1의 압축률에서 최대 79.11배의 성능 향상과 99fps의 throughput 속도를 보여준다.

• 디지털산업정보학회논문지
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• 제15권2호
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• pp.63-70
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• 2019

To increase the efficiency of task on the desk, this paper proposes a reconfigurable desk. The proposed reconfigurable desk is based on the Pin Art technology. For the design of the proposed desk, the upper surface of the desk is divided into small units, and then the user easily controls the height of the divided pieces to make desk a desired shape by using the proposed user interface. The Arduino module controls the hardware and the user interface is configured by using Android applications, making it easy for anyone to use. Through extensive experiments, the proposed system shows that various types of deformations are possible and thus the utilization is very high by mounting diverse devices.

• 제어로봇시스템학회논문지
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• 제10권3호
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• pp.261-266
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• 2004

Recently, a variety of intelligent robots are developed for the personal purpose beyond the industrial application. These intelligent robots have ranges of sensors, actuators, and control algorithms to their application. In this paper we propose a reconfigurable robot controller, $SR^2$c (The SOPC-based Reconfigurable Robot Controller), based on SOPC (System on a Programmable Chip), that can be reconfigurable easily by software. The proposed robot controller contains not only a processing module but also robot-specific IP's. To show a feasibility of the proposed robot controller, a small entertainment robot, Wizard-4 is implemented with a single chip controller as proposed in this paper.

• 제어로봇시스템학회논문지
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• 제13권5호
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• pp.422-428
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• 2007

This paper presents a neural network based adaptive control approach to a reconfigurable flight control law that keeps handling qualities in the presence of faults or failures to the control surfaces of an aircraft. This approach removes the need for system identification for control reallocation after a failure and the need for an accurate aerodynamic database for flight control design, thereby reducing the cost and time required to develope a reconfigurable flight controller. Neural networks address the problem caused by uncertainties in modeling an aircraft and pseudo control hedging deals with the nonlinearity in actuators and the reconfiguration of a flight controller. The effect of the reconfigurable flight control law is illustrated in results of a nonlinear simulation of an unmanned aerial vehicle Durumi-II.