• Korean Journal of Computational Design and Engineering
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• v.22 no.2
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• pp.129-140
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• 2017

This paper presents a systematic approach for design of timely and proper layouts of a manufacturing system facilitating reconfigurability, referred to as a reconfigurable manufacturing system. A proper methodology for design of a system layout is required for reconfiguration planning - adding or removing machines for supplying the exact capacity needed to fulfill market demands, as well as minimizing the cost of adding new machines. In this paper, theory of constraints is used to make reconfiguration manufacturing systems more cost-effective and efficiency. The proposed approach is validated by using a real industrial case. This paper suggests that the proposed study should be performed concurrently with the design of a new manufacturing system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.381-391
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• 2010

In this paper, a novel frequency reconfigurable active array antenna(RAA) system, which can be reconfigurable for three reconfigurable frequency bands, is proposed by using commercial RF MEMS switches. The MEMS switch shows excellent insertion loss, linearity, as well as isolation. So, the system performance degradation of the reconfigurable system by using MEMS switches can be minimized. The proposed frequency reconfigurable active antenna system is consisted with the noble frequency reconfigurable front-end amplifiers(RFA) with the simple reconfigurable impedance matching circuits(RMC), reconfigurable antenna elements(RAE), as well as a reconfiguration control board(RCB) for MEMS switch control. The proposed RAA system can be reconfigurable for three frequency bands, 850 MHz, 1.9 GHz, and 3.4 GHz, with $2{\times}2$ array of the RAE having broadband printed dipole antenna topology. The validity of the proposed RFA as well as RAA is also presented with the experimental results of the fabricated systems.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.174-181
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• 2004

In this paper, we review the four receiver architectures and four methods for multi-standard receiver design. Propose reconfigurable RF block can be used for both low-IF and direct conversion architecture. Also, using reconfigurable mixer method, it can be operated at $2{\sim}6$ GHz range for multi-standard receiver. It consists of wideband mixer, filter, and automatic gain control amplifier and to get wide-band operation, $2{\sim}6$ GHz, wide-band mixer use flexible input matching method. Besides, to design multi-standard receiver, LNA bank that support each standard is necessary and it has good performance to compensate the performance of wide-band mixer. Finally, we design and simulate proposed reconfigurable RF block and to prove that it has acceptable performances for various wireless standards, the LNA bank that supports both IEEE 802.11a/b/g and WCDMA is also designed and simulated with it.

• Journal of Internet Computing and Services
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• v.7 no.2
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• pp.121-136
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• 2006

Software architecture and protocols to be maintained between components for the reconfigurable SDR system is analyzed and suggest system design idea for the implementation of software. To do this, related surveys are reviews and set up the system model with the structure of embedded system. SDR system architecture is suggested with five layered structure, consisted with hardware, operating system, middle-ware, service objects and application layer. SDR system is designed to be work on the basis of Linux operating system, and aimed to be scalable and reconfigurable. It is introduced the design result of software protocol and state transition diagram for the implementations of software download function which is the most important feature in SDR.

• Journal of Institute of Control, Robotics and Systems
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• v.9 no.2
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• pp.99-106
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• 2003

A new reconfigurable model following flight control method based on direct adaptive scheme is presented. Using the timescale separation principle, both the inner-loop and the outer-loop states are controlled simultaneously. For the timescale separation assumption to be satisfied, the inner-loop model dynamics is set to be fast whereas the outer-loop model dynamics is set to be relatively slow. The stability and convergence of the proposed control law is proved by Lyapunov theorem. One of the merits of the proposed reconfigurable controller is that the FDI process and the persistent input excitation are not necessary, which is suitable for the flight control system. To evaluate the reconfiguration performance of the proposed control method, numerical simulation is performed using six degree-of-freedom nonlinear dynamics.

• Journal of IKEEE
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• v.24 no.1
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• pp.186-193
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• 2020

In this paper, we propose a multi-threading system to support reconfigurable hardware accelerators on Zynq SoC. We implement high-performance JPEG decoder with reconfigurable 2D IDCT hardware accelerators to achieve maximum performance available on the platform. In this system, up to four reconfigurable hardware accelerators synchronized with SW threads can be dynamically reconfigured to provide adaptive computing capabilities according to the given image resolution and the compression ratio. JPEG decoding is operated using images with resolutions 480p, 720p, 1080p at the compression ratio of 7:1-109:1. We show that significant performance improvements are achieved as the image resolution or the compression ratio increase. For 1080p resolution, the performance improvement is up to 79.11 times with throughput speed of 99 fps at the compression ratio 17:1.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.2
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• pp.63-70
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• 2019

To increase the efficiency of task on the desk, this paper proposes a reconfigurable desk. The proposed reconfigurable desk is based on the Pin Art technology. For the design of the proposed desk, the upper surface of the desk is divided into small units, and then the user easily controls the height of the divided pieces to make desk a desired shape by using the proposed user interface. The Arduino module controls the hardware and the user interface is configured by using Android applications, making it easy for anyone to use. Through extensive experiments, the proposed system shows that various types of deformations are possible and thus the utilization is very high by mounting diverse devices.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.3
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• pp.261-266
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• 2004

Recently, a variety of intelligent robots are developed for the personal purpose beyond the industrial application. These intelligent robots have ranges of sensors, actuators, and control algorithms to their application. In this paper we propose a reconfigurable robot controller, $SR^2$c (The SOPC-based Reconfigurable Robot Controller), based on SOPC (System on a Programmable Chip), that can be reconfigurable easily by software. The proposed robot controller contains not only a processing module but also robot-specific IP's. To show a feasibility of the proposed robot controller, a small entertainment robot, Wizard-4 is implemented with a single chip controller as proposed in this paper.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.5
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• pp.422-428
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• 2007

This paper presents a neural network based adaptive control approach to a reconfigurable flight control law that keeps handling qualities in the presence of faults or failures to the control surfaces of an aircraft. This approach removes the need for system identification for control reallocation after a failure and the need for an accurate aerodynamic database for flight control design, thereby reducing the cost and time required to develope a reconfigurable flight controller. Neural networks address the problem caused by uncertainties in modeling an aircraft and pseudo control hedging deals with the nonlinearity in actuators and the reconfiguration of a flight controller. The effect of the reconfigurable flight control law is illustrated in results of a nonlinear simulation of an unmanned aerial vehicle Durumi-II.