• Journal of the Institute of Electronics Engineers of Korea SD
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• 제42권12호
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• pp.79-90
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• 2005

In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST to improve the embedding probabilities of random-pattern-resistant-patterns. The proposed method uses a scan-cell reordering technique based on the signal probabilities of given test cubes and specific hardware blocks that increases the embedding probabilities of care bit clustered scan chain test cubes. We have developed a simulated annealing based algorithm that maximizes the embedding probabilities of scan chain test cubes to reorder scan cells, and an iterative algorithm for synthesizing the CRIN hardware. Experimental results demonstrate that the proposed CRIN BIST technique achieves complete fault coverage with lower storage requirement and shorter testing time in comparison with the conventional methods.

• Aerospace Engineering and Technology
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• 제12권2호
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• pp.131-139
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• 2013

This paper describes the design and implementation of a small avionics unit based on soft CPU. A small avionics unit is developed with the soft CPU which can be wholly implemented in FPGA using logic synthesis. Design and integration of a modular architecture for versatile, reconfigurable and re-adaptable is presented with the Nios-II processor. To gain modular architecture, both at main board and sub-board level, attention has been paid to the selection of interfaces and an adequate data and power bus.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 한국퍼지및지능시스템학회 1997년도 춘계학술대회 학술발표 논문집
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• pp.67-72
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• 1997

본 논문은 저비용이면서 정확한 제어를 수행하는 새로운 퍼지 제어기의 재구성 가능한 FPGA 시스템상의 구현을 다룬다. 제안한 퍼지 제어기 (Fuzzy Logic Controller : FLC)의 시스템 구조와 이의 VHDL 설계 및 시뮬레이션은 다른 논문에 나타나 있다. 제안한 퍼지 제어기의 구현 과정은 다음과 같다. 각 모듈은 VHDL 언어에 의해서 기술된 뒤, Synopsys사의 FPGA 컴파일러에 의해 합성된다. 합성된 각 모듈은 Xilinx사의 XactStep 6.0에 의해 최적화 및 배치, 배선이 이루어진다. 얻어진 Xilinx rawbit 파일은 VCC사의 r2h에 의해 C 언어의 header 파일 형태의 하드웨어 object로 변환된다. C언어 형태의 하드웨어 object를 포함하는 응용 제어 프로그램이 C 컴파일러에 의해 컴파일된 후, 이 실행 파일이 재구성 가능한 FPGA 시스템 상에 다운로드된다. 제안한 퍼지 제어기를 EVCI 보드 상에 동적으로 구현하여 트럭 후진 주차 제어에 사용할 때 걸리는 시간을 Synopsys사의 VHDL 시뮬레이터와 워크스테이션상에서 C언어에 의해 구현하여 트럭 후진 주차 제어에 사용할 때 걸리는 시간을 각각 비교하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제45권12호
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• pp.1-7
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• 2008

Magnetic Tunneling Junction (MTJ) has been used as a nonvolatile universal storage element mainly in memory technology. However, according to several recent studies, magneto-logic using MTJ elements show much potential in substitution for the transistor-based logic device. Magneto-logic based on MTJ can maintain the data during the power-off mode, since an MTJ element can store the result data in itself. Moreover, just by changing input signals, the full logic functions can be realized. Because of its programmability, it can embody the reconfigurable magneto-logic circuit in the rigid physical architecture. In this paper, we propose a novel 3-bit arbitrary magneto-logic circuit beyond the simple combinational logic or the short sequential one. We design the 3-bit magneto-logic which has the most complexity using MTJ elements and verify its functionality. The simulation results are presented with the HSPICE macro-model of MTJ that we have developed in our previous work. This novel magneto-logic based on MTJ can realize the most complex logic function. What is more, 3-bit arbitrary logic operations can be implemented by changing gate signals of the current drivel circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제44권9호
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• pp.10-17
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• 2007

It opens a new horizon on spintronics for the potential application of MTJ as a universal logic element, to employ the magneto-logic in substitution for the transistor-based logic device. The magneto-logic based on the MTJ element shows many potential advantages, such as high density, and nonvolatility. Moreover, the MTJ element has programmability and can therefore realize the full logic functions just by changing the input signals. This magneto-logic using MTJ elements can embody the reconfigurable circuit to overcome the rigid architecture. The established magneto-logic element has been designed and fabricated on a triple-layer MTJ. We present a novel magneto-logic structure that consists of a single layer MTJ and a current driver, which requires less processing steps with enhanced functional flexibility and uniformity. A 4-bit gray counter is designed to verify the magneto-logic functionality of the proposed single-layer MTJ and the simulation results are presented with the HSPICE macro-model of MTJ that we have developed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.165-175
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• 2010

This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

• Journal of Institute of Control, Robotics and Systems
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• 제19권4호
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• pp.328-333
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• 2013

Since a slight malfunction of control systems in a nuclear power plant may cause huge catastrophes, such control systems usually have multiple redundancy and reliable features, and their reliability and availability should be analyzed and verified thoroughly. This paper performed the reliability analysis of the SPLC (Safety Programmable Logic Controller) that is under developed as the control systems for the next generation nuclear power plant. One of the key features of SPLC is that it has multiple redundancy modes as faults happen, which means the reliability analysis for one fixed redundant model is not enough to analyze the reliability of SPLC. With considering this reconfigurable concept, FTA (Fault Tree Analysis) was used to capture fault-relationship among sub-modules. The analysis results show that MTTF (Mean Time to Fault) of SPLC is 45,080 hours, which is a about 4.5 times longer than the regulation, 10,000 hours.

• Journal of the Korean Institute of Intelligent Systems
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• 제11권8호
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• pp.746-753
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• 2001

In this paper, we review the basic concept of Evolvable Hardware first. And we examine genetic algorithm processor and hardware reconfiguration method and implementation. By considering complexity and performance of hardware at the same time, we design genetic algorithm processor using modularization and parallel processing method. And we design frame that has connection structure and logic block on FPGA, and embody reconfigurable hardware that do so that this frame may be reconstructed by RAM. Also we implemented ECANS that information processing system such as living creatures'brain using this hardware reconfiguration method. And we apply ECANS which is implemented using the concept of Evolvable Hardware to time-series prediction problem in order to verify the effectiveness.

• Journal of the Korean Institute of Intelligent Systems
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• 제9권6호
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• pp.634-643
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• 1999

This paper concerns an implementation of f~rry logic controller (FLC') on a reconfigurahle FP

• ETRI Journal
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• 제31권5호
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• pp.545-553
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• 2009

String matching is a fundamental element of an important category of modern packet processing applications which involve scanning the content flowing through a network for thousands of strings at the line rate. To keep pace with high network speeds, specialized hardware-based solutions are needed which should be efficient enough to maintain scalability in terms of speed and the number of strings. In this paper, a novel architecture based upon a recently proposed data structure called the Bloomier filter is proposed which can successfully support scalability. The Bloomier filter is a compact data structure for encoding arbitrary functions, and it supports approximate evaluation queries. By eliminating the Bloomier filter's false positives in a space efficient way, a simple yet powerful exact string matching architecture is proposed that can handle several thousand strings at high rates and is amenable to on-chip realization. The proposed scheme is implemented in reconfigurable hardware and we compare it with existing solutions. The results show that the proposed approach achieves better performance compared to other existing architectures measured in terms of throughput per logic cells per character as a metric.