• 디지털산업정보학회논문지
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• 제14권4호
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• pp.87-92
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• 2018

One of the problems with the base station equipment is that there is a large difference between the replacement time of the hardware equipment such as the base station equipment and the radio access equipment, and the evolution period of the communication standard. Therefore, the base station communication platform must be flexible enough to handle the evolving communication standards after purchase. Recent research on reconfigurable communications platforms has focused on the efficient architecture of the communications platform to meet these requirements through software downloads while still using existing hardware. This paper presents a prototype of a base station communications platform based on the ETSI standard reconfigurable architecture. The communication platform presented in this paper is implemented as an ETSI standard reconfigurable architecture using a general-purpose DSP (Digital Signal Processor). In the implemented prototype, we verify the real-time feasibility of communication protocol updates through software reconfiguration.

• 제어로봇시스템학회논문지
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• 제11권12호
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• pp.1002-1010
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• 2005

We study on the implementation of reconfigurable position control system which is based on Open Control Platform(OCP) for Unmanned Expedition Vehicles(UEV) in ubiquitous environment. The control system uses hierarchical control structure and OCP structure which contains three layers such as core OCP, reconfigurable control API(Application Programmer Interface), generic hybrid control API. The goal of our research is to implement an UEV control system using advanced software technology. As a specific control problem, we study a transition management problem between PID control and neural network control depending on fault or parameter change of the plant, i.e., UEV. The concept of the OCP-based software-enabled control can provide synergy effect by the integration of software component, middleware, network communication, and control, and thus can be applied to various systems in ubiquitous environment.

• 전기학회논문지
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• 제61권11호
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• pp.1689-1694
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• 2012

In this paper, we present a reconfigurable mobile platform (RMP) for user-specific applications. The RMP consists of a basic module and more than one extended module that offers specified functions to a portable platform based on the circumstances and purposes of the users. The extend module for specified purposes is connected to the basic module using a common interface that offers interoperability to the traditional interfaces. This paper gives the results of a survey to determine specifications of a reconfigurable mobile platform. Utilizing the results of the survey, we propose a prototype of the reconfigurable mobile platform to enable specialized functions. The design objective is to provide specialized functions required for user specific needs related to their age and physical condition. In addition, it can be used for mobile healthcare applications that are efficient in improving the user's health conditions by executing medical analysis and prescriptions.

• 방송공학회논문지
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• 제20권5호
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• pp.774-777
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• 2015

본 논문에서는 8K(7680x4320) UHD(Ultra High Definition) TV에서의 화질 향상을 위한 영상신호 처리용 프로그래머블 비디오 프로세싱 플랫폼을 세계 최초로 제안하였다. 8K 영상을 초당 60 프레임으로 처리하기 위해서는 고성능 컴퓨팅 능력과 대용량의 메모리 대역폭이 지원되어야 한다. 제안한 아키텍처에서는 입력 영상의 병렬처리를 위한 멀티 클러스터 구조, 클러스터 간이 데이터 파이프라이닝을 위한 링 데이터 패스 구조 및 필터링 연산을 위한 하드웨어 가속기로 구성되었다. 재구성형 프로세서(Reconfigurable Processor) 기반의 제안된 플랫폼은 다양한 화질향상 알고리즘을 구동할 수 있으며, UHD 방송 표준 및 디스플레이 패널 변동성에 알고리즘의 업데이트만으로 대응이 가능한 큰 장점을 갖고 있다.

• 한국멀티미디어학회논문지
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• 제10권1호
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• pp.66-73
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• 2007

SDR(Software Defined Radio) 기술은 RF 및 IF를 신호처리를 위한 고성능 디지털 신호처리 소자를 기반으로 하드웨어 수정 없이 모듈화 되어 있는 통신 플랫폼을 이용하여 소프트웨어 변경만으로 단일의 송수신 시스템을 통해 다수의 무선 통신 규격을 통합 수용하기 위한 무선 접속 기반 기술이다. 다양한 복합 네트워크 환경 하에서 구성될 다양한 통신 시스템은 각각의 무선 네트워크들 간의 쉽고 빠른 인터페이스를 보장하기 위해 재구성 가능한 SDR개념 기반의 통신 플랫폼이 요구된다. 본 논문은 이러한 SDR 기반의 플랫폼 구현을 위해 TMS320C6713 CPU를 이용한 DSP 보드, IF 신호처리를 위한 FPGA 보드와 무선랜 대역의 RF 송수신기가 결합된 형태의 통신 플랫폼을 설계 및 제작하였다. 또한, 제작된 플랫폼을 이용하여 다양한 통신방식(BPSK, QPSK, 16QAM)을 적용함으로서, 재구성 가능한 통신 단말 플랫폼의 구현을 확인하였다.

• 제어로봇시스템학회논문지
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• 제10권9호
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• pp.816-824
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• 2004

In this paper, the framework for accelerating the development of personal robots is presented, which includes the technology such as modularization with its own processing and standardization open to the other developers. Its basic elements are Module-D(Module of DRP I) characterized functionally and VM-D(Virtual Machine of DRP I) arbitrating Module-Ds. They can suggest the effective ways for integrating various robotic components and interfacing among them. Based on this framework, we developed a fully modularized personal robot called DRP I(Dynamically Reconfigurable Personal robot). Its hardware components are easily attached to and detached from the whole system. In addition, each software of the components is functionally distributed. For the materialization of the proposed idea, we mainly focus on the dynamically reconfigurable feature of DRP I.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.531-532
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• 2006

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• International Journal of Computer Science & Network Security
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• 제21권4호
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• pp.1-8
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• 2021

The subject of navigation has drawn a large interest in the last few years. Navigation problem (or path planning) finds the path between two points, source location and destination location. In smart cities, solving navigation problem is essential to all residents and visitors of such cities to guide them to move easily between locations. Also, the navigation problem is very important in case of moving robots that move around the city or part of it to get some certain tasks done such as delivering packages, delivering food, etc. In either case, solution to the navigation is essential. The core to navigation systems is the navigation algorithms they employ. Navigation algorithms can be classified into navigation algorithms that depend on maps and navigation without the use of maps. The map contains all available routes and its directions. In this proposal, we consider the first class. In this paper, we are interested in getting path planning solutions very fast. In doing so, we employ a parallel platform, Reconfigurable mesh (R-Mesh), to compute the path from source location to destination location. R-Mesh is a parallel platform that has very fast solutions to many problems and can be deployed in moving vehicles and moving robots. This paper presents two algorithms for path planning. The first assumes maps with linear streets. The second considers maps with branching streets. In both algorithms, the quality of the path is evaluated in terms of the length of the path and the number of turns in the path.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• 전기전자학회논문지
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• 제24권1호
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• pp.186-193
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• 2020

본 논문에서는 Zynq SoC 환경에서 재구성 가능한 하드웨어 가속기를 지원하는 멀티쓰레딩 시스템을 제안한다. 압축된 정지 영상의 픽셀 데이터를 복원하는 고성능 JPEG 디코더를 구현하고 2D-IDCT 함수를 재구성 가능한 하드웨어 가속기로 설계하여 성능을 검증한다. 구현된 시스템에서 최대 4개의 재구성 가능한 하드웨어 가속기는 소프트웨어 쓰레드와 동기화되어 연산을 수행할 수 있으며 이미지 해상도와 압축률에 따라 다른 성능 향상을 보인다. 1080p 해상도 영상의 경우 17:1의 압축률에서 최대 79.11배의 성능 향상과 99fps의 throughput 속도를 보여준다.