• Journal of Korea Society of Digital Industry and Information Management
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• v.14 no.4
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• pp.87-92
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• 2018

One of the problems with the base station equipment is that there is a large difference between the replacement time of the hardware equipment such as the base station equipment and the radio access equipment, and the evolution period of the communication standard. Therefore, the base station communication platform must be flexible enough to handle the evolving communication standards after purchase. Recent research on reconfigurable communications platforms has focused on the efficient architecture of the communications platform to meet these requirements through software downloads while still using existing hardware. This paper presents a prototype of a base station communications platform based on the ETSI standard reconfigurable architecture. The communication platform presented in this paper is implemented as an ETSI standard reconfigurable architecture using a general-purpose DSP (Digital Signal Processor). In the implemented prototype, we verify the real-time feasibility of communication protocol updates through software reconfiguration.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.12
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• pp.1002-1010
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• 2005

We study on the implementation of reconfigurable position control system which is based on Open Control Platform(OCP) for Unmanned Expedition Vehicles(UEV) in ubiquitous environment. The control system uses hierarchical control structure and OCP structure which contains three layers such as core OCP, reconfigurable control API(Application Programmer Interface), generic hybrid control API. The goal of our research is to implement an UEV control system using advanced software technology. As a specific control problem, we study a transition management problem between PID control and neural network control depending on fault or parameter change of the plant, i.e., UEV. The concept of the OCP-based software-enabled control can provide synergy effect by the integration of software component, middleware, network communication, and control, and thus can be applied to various systems in ubiquitous environment.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.11
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• pp.1689-1694
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• 2012

In this paper, we present a reconfigurable mobile platform (RMP) for user-specific applications. The RMP consists of a basic module and more than one extended module that offers specified functions to a portable platform based on the circumstances and purposes of the users. The extend module for specified purposes is connected to the basic module using a common interface that offers interoperability to the traditional interfaces. This paper gives the results of a survey to determine specifications of a reconfigurable mobile platform. Utilizing the results of the survey, we propose a prototype of the reconfigurable mobile platform to enable specialized functions. The design objective is to provide specialized functions required for user specific needs related to their age and physical condition. In addition, it can be used for mobile healthcare applications that are efficient in improving the user's health conditions by executing medical analysis and prescriptions.

• Journal of Broadcast Engineering
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• v.20 no.5
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• pp.774-777
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• 2015

This paper introduces the world's first programmable video-processing platform for the enhancement of the video quality of the 8K(7680x4320) UHD(Ultra High Definition) TV operating up to 60 frames per second. In order to support required computing capacity and memory bandwidth, the proposed platform implemented several key features such as symmetric multi-cluster architecture for parallel data processing, a ring-data path between the clusters for data pipelining and hardware accelerators for computing filter operations. The proposed platform based on RP(Reconfigurable Processor) processes video quality enhancement algorithms and handles effectively new UHD broadcasting standards and display panels.

• Journal of Korea Multimedia Society
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• v.10 no.1
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• pp.66-73
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• 2007

SDR technology is a fundamental wireless access technology that combines and accommodates multiple wireless communication standards in one transceiver system through just modifying software using modular communication platforms without any hardware modifications for RF and IF signal processing on the basis of high performance DSP devices. Various communication systems that are designed under diverse and complex network environments require the communication platforms on the basis of SDR supporting reorganization to guarantee simple and fast communication interfaces among the respective wireless networks. This paper introduces a main idea on the implementation of platform on the basis of SDR and a communication platform is designed for experiments that is composed of a DSP board with TMS320C6713 CPU, a FPGA board processing IF signals, and a module with RF transceiver processing wireless LAN frequency bandwidth. Various modulation schemes(BPSK, QPSK, and 16QAM) used in communication systems are applied and tested on the designed platform and the test results shows that it is possible to design a reconfigurable communication terminal platform.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.9
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• pp.816-824
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• 2004

In this paper, the framework for accelerating the development of personal robots is presented, which includes the technology such as modularization with its own processing and standardization open to the other developers. Its basic elements are Module-D(Module of DRP I) characterized functionally and VM-D(Virtual Machine of DRP I) arbitrating Module-Ds. They can suggest the effective ways for integrating various robotic components and interfacing among them. Based on this framework, we developed a fully modularized personal robot called DRP I(Dynamically Reconfigurable Personal robot). Its hardware components are easily attached to and detached from the whole system. In addition, each software of the components is functionally distributed. For the materialization of the proposed idea, we mainly focus on the dynamically reconfigurable feature of DRP I.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.531-532
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• 2006

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• International Journal of Computer Science & Network Security
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• v.21 no.4
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• pp.1-8
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• 2021

The subject of navigation has drawn a large interest in the last few years. Navigation problem (or path planning) finds the path between two points, source location and destination location. In smart cities, solving navigation problem is essential to all residents and visitors of such cities to guide them to move easily between locations. Also, the navigation problem is very important in case of moving robots that move around the city or part of it to get some certain tasks done such as delivering packages, delivering food, etc. In either case, solution to the navigation is essential. The core to navigation systems is the navigation algorithms they employ. Navigation algorithms can be classified into navigation algorithms that depend on maps and navigation without the use of maps. The map contains all available routes and its directions. In this proposal, we consider the first class. In this paper, we are interested in getting path planning solutions very fast. In doing so, we employ a parallel platform, Reconfigurable mesh (R-Mesh), to compute the path from source location to destination location. R-Mesh is a parallel platform that has very fast solutions to many problems and can be deployed in moving vehicles and moving robots. This paper presents two algorithms for path planning. The first assumes maps with linear streets. The second considers maps with branching streets. In both algorithms, the quality of the path is evaluated in terms of the length of the path and the number of turns in the path.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• Journal of IKEEE
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• v.24 no.1
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• pp.186-193
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• 2020

In this paper, we propose a multi-threading system to support reconfigurable hardware accelerators on Zynq SoC. We implement high-performance JPEG decoder with reconfigurable 2D IDCT hardware accelerators to achieve maximum performance available on the platform. In this system, up to four reconfigurable hardware accelerators synchronized with SW threads can be dynamically reconfigured to provide adaptive computing capabilities according to the given image resolution and the compression ratio. JPEG decoding is operated using images with resolutions 480p, 720p, 1080p at the compression ratio of 7:1-109:1. We show that significant performance improvements are achieved as the image resolution or the compression ratio increase. For 1080p resolution, the performance improvement is up to 79.11 times with throughput speed of 99 fps at the compression ratio 17:1.