• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.6B
• /
• pp.752-759
• /
• 2001

본 논문은 필터 뱅크의 저전력 구조와 유연성 구조를 위한 구현 방법을 제안한다. 이와 같은 특성을 갖도록 하기 위하여 블록 필터를 필터 뱅크에 사용하였다. 블록 필터를 데시메이션 필터에 적용함으로써, 블록 필터의 병렬-직렬 변화기와 다운 샘플러가 상쇄됨을 보인다. 인터폴레이션 필터에서도 마찬가지로, 업 샘플러와 블록 필터의 직렬-병렬 변환기가 상쇄되어 효율적인 구조가 만들어짐을 보인다. 더 나아가, 블록 필터를 Uniform 필터 뱅크에 적용함으로써 분석 단자 합성 단의 첫 번째 채널 필터가 모든 채널에 공유될 수 있음을 보인다. 이와 같은 공유를 통하여 계산량이 현저히 감소된 필터 뱅크를 구현할 수 있었다. 또한 블록 필터 뱅크는 필터 뱅크의 차수 변환에 따른 하드웨어의 가감이 매우 용이하여 유연성을 갖는 구조임을 보인다.

• ETRI Journal
• /
• v.31 no.6
• /
• pp.770-777
• /
• 2009

We have developed a fully functional reconfigurable optical add-drop multiplexer (ROADM) switch module using a polymer integrated photonic lightwave circuit technology. The polymer variable optical attenuator (VOA) array and digital optical switch array are integrated into one polymer PLC chip and packaged to form a 10-channel VOA integrated optical switch module. Four of these optical switch modules are used in the ROADM switch module to execute 40-channel switching and power equalization. As a wavelength division multiplexer (WDM) filter device, two C-band 40-channel athermal arrayed waveguide grating WDMs are used in the ROADM module. Optical power monitoring of each channel is carried out using a 5% tap PD. A controller and firmware having the functions of a 40-channel switch and VOA control, optical power monitoring, as well as TEC temperature control, and data communication interfaces are also developed in this study.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.787-788
• /
• 2006

본 논문에서는 적응적 재구성 필터를 이용한 심전도 신호의 잡음제거 알고리즘을 개발하고 이를 임베디드 보드 상에서 구현하였다. 구현된 시스템의 검증을 위해, 제안된 알고리즘은 PC 상에서 소프트웨어만으로 구현했을 때와 적응적 재구성 필터를 소프트웨어와 FPGA 로 구현했을 때의 실행시간 및 잡음제거 성능을 비교하였다. 실험결과 FPGA 상에서 구현된 시스템은 PC 상에서 구현된 프로그램과 비교하여 동일 잡음제거 성능을 가질 때 약 5배정도의 실행시간 향상을 보였다.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.11
• /
• pp.2845-2854
• /
• 1998

Median filter can be implemented in the binary domain based on threshold decomposition, stacking property, and linear separability. In this paper, we develop one-dimensional and two-dimensional parallel algorithms for the median filter on a reconfigurable mesh with buses(RMESH) which is suitable for VLSI implementation. And we evaluate their performance by comparing the time complexities of RMESH algorithms with those of algorithms on mesh-connected computer. When the length of M-valued 1-D signal is N and w is the window width, the RMESH algorithm is done in O(Mw) time and mesh algorithm is done in $O(Mw^2)$ time. Beside, when the size of M-valued 2-D image is $N{\times}N$ and the window size is $w{\times}w$, our algorithm on $N{\times}N$ RMESH can be computed in O(Mw) time which is a significant improvement over the $O(Mw^2)$ complexity on $N{\times}N$ mesh.

• The KIPS Transactions:PartC
• /
• v.11C no.7 s.96
• /
• pp.951-958
• /
• 2004

Nowadays NGN is developed for supporting the e-Commerce, Internet trading, e-Government, e-mail, virtual-life and multimedia. Internet gives us the benefit of remote access to the information but causes the attacks that can break server and modify information. Since 2000 Nimda, Code Red Virus and DSoS attacks are spreaded in Internet. This attack programs make tremendous traffic packets on the Internet. In this paper, we designed and developed the Bandwidth Controller in the gateway systems against the bandwidth saturation attacks. This Bandwidth con-troller is implemented in hardware chipset(FPGA) Virtex II Pro which is produced by Xilinx and acts as a policing function. We reference the TBF(Token Bucket Filter) in Linux Kernel 2.4 and implemented this function in HDL(Hardware Description Language) Verilog. This HDL code is synthesized in hardware chipset and performs the gigabit traffic in real time. This policing function can throttle the traffic at the rate of band width controlling policy in bps speed.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.18 no.1
• /
• pp.21-31
• /
• 2017

In this paper, the Zynq system-on-chip (SoC) platform is used to design an adaptive noise reduction and edge-detection system using partial reconfiguration. Filters are implemented in a partially reconfigurable (PR) region to provide high computational complexity in real-time, 1080p video processing. In addition, partial reconfiguration enables better utilization of hardware resources in the embedded system from autonomous replacement of filters in the same PR region. The proposed edge-detection system performs adaptive noise reduction if the noise density level in the incoming video sequences exceeds a given threshold value. Results of implementation show that the proposed system improves the accuracy of edge-detection results (14~20 times in Pratt's Figure of Merit) through self-reconfiguration of filter bitstreams triggered by noise density level in the video sequences. In addition, the ZyCAP controller implemented in this paper enables about 2.1 times faster reconfiguration when compared to a PCAP controller.