• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.261-273
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• 2016

Reconfigurable finite impulse response (FIR) filters whose filter coefficients and filter order change dynamically during run-time play an important role in the software defined radio (SDR) systems, multi-channel filters, and digital up/down converters. However, there are not many reports on such reconfigurable designs which can support dynamic variation of filter order and filter coefficients. The purpose of this paper is to provide an architectural solution for the FIR filters to support run-time variation of the filter order and filter coefficients. First, two straightforward designs, namely, (i) single-MAC based design and (ii) full-parallel design are presented. For large variation of the filter order, two designs based on (iii) folded structure and (iv) fast FIR algorithm are presented. Finally, we propose (v) high throughput design which provides significant advantage in terms of hardware and/or time complexities over the other designs. We compare complexities of all the five structures, and provide the synthesis results for verification.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.309-311
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• 2005

In general, for specific applications, customized hardware showed better performance than general processor in terms of processing time and power consumption. However, customized hardware systems have lacks of flexibility in nature and it leads the difficulties for debugging and architecture level revision for performance enhancement. To solve this problem, reconfigurable hardware is developed. Proposed reconfigurable hardware architecture for FIR filter system can easily change the architecture of filter blocks including filter tap size and their signal path. Proposed FIR filter architecture was implemented on FPGA using several MUXs and registers and it showed the reconfigurablility and reusability in several examples.

• 대한전자공학회논문지SD
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• 제44권4호
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• pp.97-102
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• 2007

본 논문은 부분 재구성 설계방법을 이용하여 Xilinx Virtex4 FPGA로 구현된 재구성형 FIR 필터의 구조를 제시한다. 설계한 재구성형 FIR 필터는 저 전력 소비, 자율적 채택, 재구성 능력 등 모든 목적에 부합하는 재구성 가능한 디지털 신호처리 구조이며, 다양한 주파수 응답에 적용 할 수 있는 FIR 필터이다. 구현된 재구성형 FIR 필터는 재구성 모듈의 추가 또는 제거를 통한 설계의 유연성과 면적 효율성을 보장하며, 다양한 차수의 필터연산 수행이 가능하다. 제안된 부분 재구성형 FIR 필터는 기존 FIR 필터의 설계방법과 비교하여, 면적 효율성, 설계의 유연성 및 구성 시간의 향상을 보인다.

• Journal of electromagnetic engineering and science
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• 제16권3호
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• pp.164-168
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• 2016

A dual-band through-the-wall imaging radar receiver for a frequency-modulated continuous-wave radar system was designed and fabricated. The operating frequency bands of the receiver are S-band (2-4 GHz) and X-band (8-12 GHz). If the target is behind a wall, wall-reflected waves are rejected by a reconfigurable $G_m-C$ high-pass filter. The filter is designed using a high-order admittance synthesis method, and consists of transconductor circuits and capacitors. The cutoff frequency of the filter can be tuned by changing the reference current. The receiver system is fabricated on a printed circuit board using commercial devices. Measurements show 44.3 dB gain and 3.7 dB noise figure for the S-band input, and 58 dB gain and 3.02 dB noise figure for the X-band input. The cutoff frequency of the filter can be tuned from 0.7 MHz to 2.4 MHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.531-532
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• 2006

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• 대한기계학회논문집A
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• 제33권5호
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• pp.455-462
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• 2009

This paper presents design concepts of a reconfigurable mobile robot for both of indoor and outdoor applications. A linkage mechanism and wheel-in-motors give the proposed mobile robot various driving modes in maneuver and good adaptability to irregular surface. Since the mobile robot receives multiple sensor signals from odometers and an orientation sensor, states related to the position and the orientation of the mobile robot are optimally estimated by an extended Kalman filter. Simulations and experimental results show that the performance of dead reckoning on estimating the pose of a mobile robot can be improved remarkably by the optimal state observer.

• 전기전자학회논문지
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• 제17권4호
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• pp.418-427
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• 2013

본 논문에서는 H.264/AVC 비디오 코덱용 디블록킹 필터의 병렬 알고리즘을 제안한다. 디블록킹 필터는 BS(boundary strength)에 따라 다른 필터 연산을 수행하며, 각 필터 연산은 다양한 조건 연산을 필요로 한다. 또한 각 경계면의 연산 순서가 정해져 있기 때문에 병렬 처리가 쉽지 않다. 본 논문에서 제안하는 디블록킹 필터 알고리즘은 최근에 소개된 1-D CGRA (coarse grained reconfigurable architecture)인 PRAGRAM (pipelined reconfigurable arrays with assistant manager groups)에서 처리된다. 디블록킹 필터 연산은 PRAGRAM의 단방향 파이프라인 PE 배열 구조를 이용하여 각 필터 연산을 고속으로 수행하고, dynamic reconfiguration 및 conditional reconfiguration을 이용하여 필터 선택과 조건 연산을 효율적으로 처리한다. 디블록킹 필터의 병렬 알고리즘은 매크로블록 당 225 사이클을 소요한다. 이는 동작주파수 150 MHz에서 full HD급 영상을 처리할 수 있는 성능이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권3호
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• pp.166-176
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• 2007

Radio frequency (RF) microelectromechanical systems (MEMS) have been pursued for more than a decade as a solution of high-performance on-chip fixed, tunable and reconfigurable circuits. This paper reviews our research work on RF MEMS switches and switching circuits in the past five years. The research work first concentrates on the development of lateral DC-contact switches and capacitive shunt switches. Low insertion loss, high isolation and wide frequency band have been achieved for the two types of switches; then the switches have been integrated with transmission lines to achieve different switching circuits, such as single-pole-multi-throw (SPMT) switching circuits, tunable band-pass filter, tunable band-stop filter and reconfigurable filter circuits. Substrate transfer process and surface planarization process are used to fabricate the above mentioned devices and circuits. The advantages of these two fabrication processes provide great flexibility in developing different types of RF MEMS switches and circuits. The ultimate target is to produce more powerful and sophisticated wireless appliances operating in handsets, base stations, and satellites with low power consumption and cost.

• Current Optics and Photonics
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• 제2권6호
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• pp.519-524
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• 2018

We propose a transverse load sensor with reconfigurable measurement accuracy based on a microwave photonic filter in the $K_u$ band, incorporating a polarization-maintaining fiber Bragg grating. A prototype sensor with a reconfigurable measurement accuracy tuning range from 6.09 to 9.56 GHz/(N/mm), and corresponding minimal detectable load range from 0.0167 to 0.0263 N/mm, is experimentally demonstrated. The results illustrate that up to 40% manufacturing error in the grating length can be dynamically calibrated to the same corresponding measurement accuracy for the proposed transverse load sensor, by controlling the semiconductor optical amplifier's injection current in the range of 154 to 419 mA.