• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.101-103
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• 2004

Expansible & Reconfigurable Neuro Informatics Engine(ERNIE) is effective in reconfigurability and extensibility. But ERNIE have the problem which have limited performance in initial network. To solve this problem, the constructive module using the reconfigurable ERNIE is implemented in simulation model. In this paper, simulation results on sonar data are showed that ERNIE using the constructive module obtains the better performance compared to ERNIE without it.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.145-149
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• 2015

A reconfigurable lighting engine for widely used lighting models is proposed for low-power GPU shaders. Conventionally, lighting operations that involve many complex arithmetic operations were calculated by the shader programs on the GPU, which led to a significant energy overhead. In this letter, we propose a lighting engine to improve the energy-efficiency by supporting the widely used advanced lighting models in hardware. It supports the Blinn-Phong, Oren-Nayar, and Cook-Torrance models, by exploiting the logarithmic arithmetic and optimizing the trigonometric function evaluations for the energy-efficiency. Experimental results demonstrate 12.7%, 42.5%, and 35.5% reductions in terms of power-delay product from the shader program implementations for each lighting model. Moreover, our work shows 10.1% higher energy-efficiency for the Blinn-Phong model compared to the prior art.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.39-48
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• 2005

This paper proposes a reconfigurable coprocessor for communication systems, which can perform high speed computations and various functions. The proposed reconfigurable coprocessor can easily implement communication operations, such as scrambling, interleaving, convolutional encoding, Viterbi decoding, FFT, etc. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18$\mu$m standard cell library. The gate count is about 35,000 gates and the critical path is 3.84ns. The proposed coprocessor can reduced about $33\%$ for FFT operations and complex MAC, $37\%$ for Viterbi operations, and $48\%\~84\%$ for scrambling and convolutional encoding for the IEEE 802.11a WLAN standard compared with existing DSPs. The proposed coprocessor shows Performance improvements compared with existing DSP chips for communication algorithms.

• Journal of the Optical Society of Korea
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• v.16 no.1
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• pp.13-16
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• 2012

We demonstrate an optical gate architecture using a single SOA to perform AND, OR and NOT logic functions. Simple reconfigurable all-optical logic operations are implemented using RZ modulated signals at 40 Gb/s. Contrast ratio and extinction ratio values have been analysed for the different types of logic gates. Maximum extinction ratio and contrast ratio achieved are 19dB and 17.2 dB respectively. Simple structure and potential for integration makes this architecture an interesting approach in photonic computing and optical signal processing.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1187-1188
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• 2008

An area of research called evolvable hardware has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. In this paper, we have studied and surveyed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm(GA) hardware, reconfigurable hardware logic, and the control logic. In this paper, we describe the architecture, functions of the chip.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.1
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• pp.10-18
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• 2007

Mobile communication devices such as PDAs, cellular phones, etc., need to perform several kinds of computation-intensive functions including H.264 encoding/decoding and 3D graphics processing. In this paper, new reconfigurable architecture is described, which can perform either motion estimation for H.264 or rendering for 3D graphics. The proposed motion estimation techniques use new efficient SAD computation ordering, DAU, and FDVS algorithms. The new approach can reduce the computation by 70% on the average than that of JM 8.2, without affecting the quality. In 3D rendering, midline traversal algorithm is used for parallel processing to increase throughput. Memories are partitioned into 8 blocks so that 2.4Mbits (47%) of memory is shared and selective power shutdown is possible during motion estimation and 3D graphics rendering. Processing elements are also shared to further reduce the chip area by 7%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.5
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• pp.521-524
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• 2015

This letter presents a selective wireless power transfer architecture using a reconfigurable multi-port amplifier. The proposed wireless power transfer architecture is composed of a phase shifter part controlled by FPGA, two class-E power amplifiers, a four-port power combiner and two coil loads. Depending on the phase control of FPGA, the power ratio of outputs at the two coil loads becomes 1:1, 2:0 and 0:2. The manufactured system has delivered 1W DC power to loads at 125 kHz. The total DC-to-DC conversion efficiency shows more than 40 % including PA efficiency of 79 %.

• Journal of IKEEE
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• v.17 no.4
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• pp.418-427
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• 2013

In this paper, we propose a parallel deblocking filter algorithm for H.264/AVC video standard. The deblocking filter has different filter processes according to boundary strength (BS) and each filter process requires various conditional calculations. The order of filtering makes it difficult to parallelize deblocking filter calculations. The proposed deblocking filter algorithm is performed on PRAGRAM which is a 1-D coarse grained reconfigurable architecture (CGRA). Each filter calculation is accelerated using uni-directional pipelined architecture of PRAGRAM. The filter selection and the conditional calculations are efficiently performed using dynamic reconfiguration and conditional reconfiguration. The parallel deblocking filter algorithm uses 225 cycles to process a macroblock and it can process a full HD image at 150 MHz.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.4
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• pp.81-87
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• 2016

Recently, as the heterogeneous network (HetNet) has been deployed widely to support various kinds of Radio Access Networks(RANs) with a combination of Macro, Pico, and/or Femto cells, research and standardization efforts have been very active regarding the concept of Licensed Shared Access (LSA) for supporting spectrum sharing. In order for a mobile device to efficiently support the spectrum sharing, the mobile device shall be reconfigurable, meaning that its radio application code has to be adaptively changed in accordance with the hopping of desired spectral band. Especially, Working Group 2 (WG2) of Technical Committee (TC) Reconfigurable Radio System (RRS) of European Telecommunications Standards Institute (ETSI) has been a main driving force for developing standard architecture for Multi-mode Mobile Device (MD) that can be applied to the LSA system. In this paper, we introduce the Multi-mode MD architecture for supporting LSA-based spectrum sharing. An implementation of a test-bed of Multi-mode MD is presented in order to verify the feasibility of the standard MD architecture for the purpose of LSA-based spectrum sharing through various experimental tests.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.61-70
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• 2004

The operation mode of neural network is divided into learning and recognition process. Learning is updating process of weight until neural network archives target result from input pattern. Recognition is arithmetic process of input pattern and weight. Traditional inner product process is focused to improve processing speed and hardware complexity. There is no hardware architecture to distinguish between loaming and recognition mode of neural network. In this paper we propose the new architecture of low power inner product processor for reconfigurable neural network. The proposed architecture is similar with bit-serial inner product processor on learning mode. It have several advantages which are fast processing base on bit-level, suitability of hardware implementation and pipeline architecture to compute data. And proposed architecture minimizes active units and reduces consumption power on recognition mode. Result of simulation shows that active units is depend on bit representation of weight, but we can reduce active units about 50 precent.