• Journal of the Korean Graphic Arts Communication Society
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• v.30 no.3
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• pp.23-33
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• 2012

We studied simultaneously the electronically written data affected in the use of thermal transfer discs and the recoding strategy between recoding drives for the stable long term preservation of optical discs which are commonly used in an electronic data storage device. The most important thing in the archiving preservation might be a choice of a device, however the use of thermal transfer recording discs is not good for long term data preservation because the thermal effect on the recoding data is critical which means that the data are recorded not under best condition but under bad condition. We inspect the strategies of recoding data from 12 brands of optical discs and drives of 7 brands and it turns out the recoding strategy is needed first for the long term preservation of electronic recording data. Thus, without affecting data quality and deformation of optical discs, the choice of optimal disc and drive in recoding data will be a solution for the long term preservation of recoding data.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.71-80
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• 1995

The usual approach for desinging a fast multiplier involves finding a way to quickly add up all the partial products, based on parital product recoding scheme and carry-save addition. This paper describes theoretical medels for area and time complexities of Multibit Reconding Paralle Multiplier (MRPM), which is a generalization of the modified Booth recoding scheme. Based on the proposed models, time performance, hardware requirements and area-time efficiency are analyzed in order to determine optimal recoding size for very large scale integration (VLSI) realization of the MRPM. Some simulation results show that the MRPM with large multiplier and multiplicand size has optimal area-time efficiency at the recoding size of 4-bit.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.3
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• pp.587-601
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• 2016

In this paper we suggest method for scalar recoding which is both secure against SPA and DPA. Suggested method is countermeasure to power analysis attack through scalar recoding using negative expression. Suggested method ensures safety of SPA by recoding the operation to apply same pattern to each digit. Also, by generating the random recoding output according to random number, safety of DPA is ensured. We also implement precomputation table and modified scalar addition algorithm for addition to protect against SPA that targets digit's sign. Since suggested method itself can ensure safety to both SPA and DPA, it is more effective and efficient. Through suggested method, compared to previous scalar recoding that ensures safety to SPA and DPA, operation efficiency is increased by 11%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.5
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• pp.1099-1103
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• 2016

The user's secret key can be retrieved by the leakage informations of power consumption occurred during the execution of scalar multiplication for elliptic curve cryptographic algorithm which can be embedded on a security device. Recently, a carry random recoding method is proposed to prevent simple power and differential power analysis attack by recoding the secret key. In this paper, we show that this recoding method is still vulnerable to the differential power analysis attack due to the limitation of the size of carry bits, which is a different from the original claim.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2001.11a
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• pp.199-199
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• 2001

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.6
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• pp.1361-1373
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• 2016

Recently the need for user authentication with increasing, there are a variety of mechanisms, such as password, graphic authentication, token, biometrics and multiple authentication. in particular, the data of the 2-dimensional(2D) factors such as password, graphic authentication, biometrics is used because of the convenience. The stored information is problematic in that additional data recording needs to be performed whenever authentication data is updated. Furthermore, this storage method is problematic in that the time it takes to perform authentication increases because the time it takes to compare storage data with authentication data increases in proportion to an increase in the amount of the storage data. Accordingly, authentication through the rapid comparison of storage data with authentication data is a very important factor in data recording and authentication technology using memory. Using the three-dimensional(3D) optical memory by variously changing the recoding elements during recoding of data constitutes the way that multiple recoding different data storage. This enables high-density recoding in this way, and by applying the possible parallel processing at the time of recording and restoring method, provided that it is possible to quickly record and restore the data. In addition, each time to solve problems that require additional data recorded by a combination of the stored data record in the old data using a combination of the authentication. The proposed mechanism is proposed an authentication method using scheme after the recoding data in 3D optical memory to apply the conditions corresponding to the recoding condition when restoring the recorded data and through the experiment it was confirmed possible application as an authentication mechanism.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.686-689
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• 2009

This paper describes a scalar multiplier for Elliptic curve cryptography. The scalar multiplier has 163-bits key size which supports the specifications of smart card standard. To reduce the computational complexity of scalar multiplication on finite field $GF(2^{163})$, the Non-Adjacent-Format (NAF) conversion algorithm based on complementary recoding is adopted. The scalar multiplier core synthesized with a $0.35-{\mu}m$ CMOS cell library has 32,768 gates and can operate up to 150-MHz@3.3-V. It can be used in hardware design of Elliptic curve cryptography processor for smart card security.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1994.06a
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• pp.409-412
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• 1994

• Proceedings of the Optical Society of Korea Conference
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• 2001.08a
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• pp.64-65
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• 2001