• E2M - 전기 전자와 첨단 소재
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• 제7권5호
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• pp.376-382
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• 1994

In this study we developed a program(DEVSIM) to simulate the two dimensional distribution of the electrostatic potential and the electric field of the arbitrary structure consisting of GaAs/AlGaAs semiconductor and metal as well as dielectric. By the comparision of the electric field distribution of GaAs MESFETs with the various recess gates we proposed a suitable device structure to improve the breakdown characteristics of MESFET. According to the results of simulation the breakdown characteristics were improved as the thickness of the active epitaxial layer was decreased. And the planar structure, which had the highly doped layer under the drain for the ohmic contact, was the worst because the highly doped layer prevented the space charge layer below the gate from extending to the drain, which produced the narrow spaced distribution of the electrostatic potential contours resulting in the high electric field near the drain end. Instead of the planar structure with the highly doped drain the recess gate structure having the highly doped epitaxial drain layer show the better breakdown characteristics by allowing the extention of the space charge layer to the drain. Especially, the structure in which the part of the drain epitaxial layer near the gate show the more improvement of the breakdown characteristics.

• ETRI Journal
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• 제27권3호
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• pp.304-311
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• 2005

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric-defined process. This process was utilized to fabricate $0.12\;{\mu}m\;{\times}\;100 {\mu}m$ T-gate PHEMTs. A two-step etch process was performed to define the gate footprint in the $SiN_x$. The $SiN_x$ was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T-gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross-sectional area of the gate and its mechanically stable structure. From s-parameter data of up to 50 GHz, an extrapolated cut-off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the $SiN_x$) with sample A (dry etching for the $SiN_x$), we observed an 62.5% increase of the cut-off frequency. This is believed to be due to considerable decreases of the gate-source and gate-drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.

• 반도체디스플레이기술학회지
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• 제12권3호
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• pp.23-27
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• 2013

This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess structures has been simulated and analyzed for the breakdown of the devices with the InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2V to almost 4V and that the saturation current at gate voltage of 0V is reduced from 90mA to 60mA at drain voltage of 2V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier layer and the $Si_3N_4$ passivation layer deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer. In the paper, the fully-recessed asymmetric gate-recess structure at the drain side shows the on-breakdown voltage enhancement from 2V to 4V in the MHEMTs.

• 전기학회논문지
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• 제56권9호
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• pp.1614-1618
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• 2007

We have demonstrated the experimental results to obtain the immunity of FN (Fowler Nordheim) stress for S-RCAT (Spherical-Recess Cell Array Transistor) which has been employed to meet the requirements of data retention time and propagation delay time for sub-100-nm mobile DRAM (Dynamic Random Access Memory). Despite of the same S-RCAT structure, the immunity of FN stress of S-RCAT depends on the process condition of gate oxidation. The S-RCAT using DPN (decoupled plasma nitridation) process showed the different degradation of device properties after FN stress. This paper gives the mechanism of FN-stress degradation of S-RCAT and introduces the improved process to suppress the FN-stress degradation of mobile DRAM.

• Korean Chemical Engineering Research
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• 제60권2호
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• pp.313-319
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• 2022

HfO₂을 게이트 산화막으로 갖는 AlGaN/GaN 기반 고이동도 전계효과 트랜지스터(high electron mobility transistor, HEMT)의 노멀리 오프(normally-off) 작동 구현을 위하여 게이트 리세스(gate-recess) 깊이에 따른 소자 특성이 시뮬레이션을 통하여 분석되었다. 전통적인 HEMT 구조, 3 nm의 두께를 갖는 게이트 리세스된 HEMT 구조, 게이트 영역에 AlGaN 층을 갖지 않는 HEMT 구조가 모사되었다. 전통적인 HEMT 구조는 노멀리 온(normally-on) 특성을 나타내었으며, 0 V의 게이트 전압 및 15 V의 드레인 전압 환경에서 0.35 A의 드레인 전류 특성을 나타내었다. 3 nm의 두께를 갖는 게이트 리세스된 HEMT 구조는 2DEG(2-dimensional electron gas) 채널의 전자 농도 감소로 인해, 같은 전압 인가 조건에서 0.15 A의 드레인 전류 값을 보였다. 게이트 영역에 AlGaN 층을 갖지 않는 HEMT 구조는 뚜렷한 노멀리 오프 동작을 나타내었으며, 0 V의 동작전압 값을 확인할 수 있었다.

• 반도체디스플레이기술학회지
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• 제12권4호
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• pp.21-25
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• 2013

This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to 4 V in the previous work. This is because the surface effect at the drain side decreases the channel current and the impact ionization in the channel at high drain voltage. In order to increase the breakdown voltage at the same asymmetric gate-recess structure, the InGaAs channel structure is replaced with the InGaAs/InP composite channel in the simulation. The simulation results with InGaAs/InP channel show that the breakdown voltage increases to 6V in the MHEMT as the current decreases. In this paper, the simulation results for the InGaAs/InP channel are shown and analyzed for the InGaAs/InP composite channel in the MHEMT.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.17-20
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• 2000

We have enhanced the yield of 0.25 ${\mu}{\textrm}{m}$ T-gate $Al_{0.25}$G $a_{0.75}$As/I $n_{0.2}$G $a_{0.8}$As P-HEMT using three-layer E-beam lithography process and selective etching process. The three-layer resist structure (PMMA/copolymer/ PMMA=2000 $\AA$/3000 $\AA$/2000 $\AA$) and three developers (Benzene：IPA=1：1,Methanol：IPA =1：1,MIBK：IPA=1：3) were used for fabrication of a wide-head T-gate by the conventional double E-beam exposure technology. Also 1 wt% citric acid： $H_2O$$_2$：N $H_{4}$OH(200m1：4ml：2.2ml) solution were used for uniform gate recess. The etching selectivity of GaAs over $Al_{0.25}$G $a_{0.75}$As is measured to be 80. So these P-HEMT processes can be used in X-band MMIC LNA fabrication.ion.ion.ion.

• 한국전기전자재료학회논문지
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• 제33권2호
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• pp.99-104
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• 2020

In this study, we fabricated a metamorphic high-electron-mobility transistor (mHEMT) device with a T-type gate structure for the implementation of W-band monolithic microwave integrated circuits (MMICs) and investigated its characteristics. To fabricate the mHEMT device, a recess process for etching of its Schottky layer was applied before gate metal deposition, and an e-beam lithography using a triple photoresist film for the T-gate structure was employed. We measured DC and RF characteristics of the fabricated device to verify the characteristics that can be used in W-band MMIC design. The mHEMT device exhibited DC characteristics such as a drain current density of 747 mA/mm, maximum transconductance of 1.354 S/mm, and pinch-off voltage of -0.42 V. Concerning the frequency characteristics, the device showed a cutoff frequency of 215 GHz and maximum oscillation frequency of 260 GHz, which provide sufficient performance for W-band MMIC design and fabrication. In addition, active and passive modeling was performed and its accuracy was evaluated by comparing the measured results. The developed mHEMT and device models could be used for the fabrication of W-band MMICs.

• 한국진공학회지
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• 제22권6호
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• pp.335-340
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• 2013

본 논문은 InP 식각정지층을 갖는 MHEMT 소자의 항복전압을 증가시키기 위한 시뮬레이션 설계 논문이다. MHEMT 소자의 게이트 리세스 구조 및 채널 구조를 변경하여 시뮬레이션을 수행하였고 비교 분석하였다. MHEMT 소자의 드레인 측만을 완전히 제거한 비대칭 게이트 리세스 구조인 경우 $I_{dss}$ 전류가 90 mA에서 60 mA로 줄어들지만 항복 전압은 2 V에서 4 V로 증가함을 확인하였다. 이는 $Si_3N_4$ 보호층과 InAlAs 장벽층 사이의 계면에서 형성되는 전자-포획 음의 고정전하로 인해 채널층에서의 전자 공핍이 심화되어 나타나는 현상으로 이는 채널층의 전류를 감소시켜 충돌이온화를 적게 형성시켜 항복전압을 증가시킨다. 또한, 동일한 구조의 비대칭 게이트 리세스 구조에서 채널층을 InGaAs/InP 복합 채널로 바꾸어 설계한 구조에서는 항복전압이 5 V로 증가하였다. 이는 높은 드레인 전압에서 InP 층의 적은 충돌이온화와 이동도로 인해 전류가 더 감소했기 때문이다.

• 전자통신동향분석
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• 제38권6호
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• pp.52-61
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• 2023

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.