• 제어로봇시스템학회논문지
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• 제5권1호
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• pp.115-121
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• 1999

Advanced digital computer technology enables the computer-based controllers to replace the traditional analog controllers used in factory automations. This replacement, however, brings up the side effects caused by the quantization error and non-real-time execution of control software. This paper describes the structure of real-time simulator and controller that can be used for design and verification of real-time digital controllers. The virtual machine concept adopted by the proposed real-time simulator makes the proposed simulator be independent from the specific hardware platforms. The proposed system can also be used in the loosely coupled distributed environments connected through local area network using real-time message passing algorithm and virtual data table based on the shared memory mechanism.

• 대한의용생체공학회:의공학회지
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• 제16권3호
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• pp.317-324
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• 1995

A need exists for the accurate identification of time series models having time varying parameters, as is important in the case of real time identification of nonstationary EMG signal. Thls paper describes real time identification and muscle fatigue monitoring method of nonstationary EMG signal. The method is composed of the efficient identifier which estimates the autoregressive parameters of nonstationary EMG signal model, and its real time implementation by using T805 parallel processing computer. The method is verified through experiment with real EMG signals which are obtained from surface electrode. As a result, the proposed method provides a new approach for real time Implementation of muscle fatigue monitoring and the execution time is 0.894ms/sample for 1024Hz EMG signal.

• Journal of Computing Science and Engineering
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• 제1권1호
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• pp.56-73
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• 2007

Demands have been growing in safety-critical application fields for producing networked real-time embedded computing (NREC) systems together with acceptable assurances of tight service time bounds (STBs). Here a service time can be defined as the amount of time that the NREC system could take in accepting a request, executing an appropriate service method, and returning a valid result. Enabling systematic composition of large-scale NREC systems with STB certifications has been recognized as a highly desirable goal by the research community for many years. An appealing approach for pursuing such a goal is to establish a hard-real-time (HRT) component model that contains its own STB as an integral part. The TMO (Time-Triggered Message-Triggered Object) programming scheme is one HRT distributed computing (DC) component model established by the first co-author and his collaborators over the past 15 years. The TMO programming scheme has been intended to be an advanced high-level RT DC programming scheme that enables development of NREC systems and validation of tight STBs of such systems with efforts far smaller than those required when any existing lower-level RT DC programming scheme is used. An additional goal is to enable maximum exploitation of concurrency without damaging any major structuring and execution approaches adopted for meeting the first two goals. A number of previously untried program structuring approaches and execution rules were adopted from the early development stage of the TMO scheme. This paper presents new concrete justifications for those approaches and rules, and also discusses new extensions of the TMO scheme intended to enable further exploitation of concurrency in NREC system design and programming.

• 정보처리학회논문지A
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• 제16A권6호
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• pp.489-500
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• 2009

네트워크 기반 로봇에서 로봇은 한정된 자원을 가지며 서비스에 따라 필요로 하는 입출력 장치와 컴퓨팅 능력 및 응답 실시간성이 다르다. 본 논문에서는 네트워크 기반 로봇에서 로봇이 다양한 서비스를 효율적으로 수행하고 서비스의 실시간성을 제공하도록 하기 위하여 서비스 실 행 컨텍스트를 동적으로 관리하는 방법을 제안한다. 실제 네트워크 기반 로봇에 적용하여 실험한 결과, 제안한 방법은 서비스 실행의 실시간 응답성을 만족하며 로봇의 자원 사용률을 향상시켰다. 제안한 방법은 서비스 실행 컨텍스트에 대한 변경이 용이하므로 센서 및 새로운 서비스 에 대한 확장성과 융통성을 제공하며 로봇 서비스의 재사용성을 증대시킨다.

• 한국정보처리학회논문지
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• 제6권9호
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• pp.2533-2539
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• 1999

결험 허용(fault olerant) 방법에는 두 개의 시스템으로 같은 직업을 수행하게 하는 이중계(duplex) 시스템과, 체크포인트를 두어 결함 발생 시 rollback 하는 checkpoint & rollback 시스템이 있다. 기존 결함 허용 시스템에서는 요구되는 신뢰성을 유지하며 테스크의 수행시간을 단축시키는데 주안점을 두었지만 시간제약을 갖는 실시간 응용 분야에서는 신뢰성 유지와 정해진 시간 이내에 테스크를 종료시키는 것이 더욱 중요하다. 본 논문에서는 이들 결함 허용 시스템을 실시간 응용 측면에서 비교 분석하였다.

• Journal of Computing Science and Engineering
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• 제5권1호
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• pp.1-18
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• 2011

As the first step toward real-time multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst-case shared L2 instruction cache misses by considering the inter-thread instruction conflicts. Also, the worst-case execution time (WCET) of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.243-248
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• 2005

The UAV (Unmanned Aerial Vehicle) systems like unmanned autonomous helicopters are used in various missions of flight navigation and used to collect the environmental information of the surroundings. To realize the full functionalities of the UAV, the software part becomes a challenging problem. In this paper embedded real-time software architecture for unmanned autonomous helicopter is proposed that guarantee real-time performance of hard-real time tasks and re-configurability of soft-real time and non-real time tasks. The proposed software architecture has four layers: hardware, execution, service agent and remote user interface layer according to the reactiveness level for external events. In addition, the layered separation of concurrent tasks makes different kinds of mission reconfiguration possible in the system. An Unmanned autonomous helicopter system was implemented (Kyosho RC Helicopter) in our lab to test and evaluate the performance of the proposed system.

• ETRI Journal
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• 제29권3호
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• pp.270-280
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• 2007

In Linux, real-time tasks are supported by separating real-time task priorities from non-real-time task priorities. However, this separation of priority ranges may not be effective when real-time tasks make the system calls that are taken care of by the kernel threads. Thus, Linux is considered a soft real-time system. Moreover, kernel threads are configured to have static priorities for throughputs. The static assignment of priorities to kernel threads causes trouble for real-time tasks when real-time tasks require kernel threads to be invoked to handle the system calls because kernel threads do not discriminate between real-time and non-real-time tasks. We present a dynamic kernel thread scheduling mechanism with weighted average priority inheritance protocol (PIP), a variation of the PIP. The scheduling algorithm assigns proper priorities to kernel threads at runtime by monitoring the activities of user-level real-time tasks. Experimental results show that the algorithms can greatly improve the unexpected execution latency of real-time tasks.

• Journal of Computing Science and Engineering
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• 제9권2호
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• pp.51-72
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• 2015

Time predictability is crucial in hard real-time and safety-critical systems. Cache memories, while useful for improving the average-case memory performance, are not time predictable, especially when they are shared in multicore processors. To achieve time predictability while minimizing the impact on performance, this paper explores several time-predictable scratch-pad memory (SPM) based architectures for multicore processors. To support these architectures, we propose the dynamic memory objects allocation based partition, the static allocation based partition, and the static allocation based priority L2 SPM strategy to retain the characteristic of time predictability while attempting to maximize the performance and energy efficiency. The SPM based multicore architectural design and the related allocation methods thus form a comprehensive solution to hard real-time multicore based computing. Our experimental results indicate the strengths and weaknesses of each proposed architecture and the allocation method, which offers interesting on-chip memory design options to enable multicore platforms for hard real-time systems.

• 전기전자학회논문지
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• 제22권1호
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• pp.6-13
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• 2018

고신뢰 CPS 개발을 위해서는 M&S는 매우 중요하다. 각각의 CPS 시스템의 다른 부분을 모델링하기 위해 각각의 다른 시뮬레이션 프로그램들을 사용하기 때문에 어떤 CPS 전체 시스템을 하나의 시뮬레이션 툴에서 모델링하기는 쉽지 않다. FMI는 다른 시뮬레이션 툴들 간에 M&S를 위한 표준이다. 또한, DDS는 대규모의 실시간 데이터 전송에 적합한 통신 미들웨어이다. 따라서 이 논문에서는 DDS를 이용하는 FMI기반의 CPS 실시간 분산 시뮬레이션 프레임워크를 제안한다. 제안하는 프레임워크의 성능 평가를 위해서 IEEE HLA/RTI와 OMG DDS 미들웨어를 사용해서 분산 시뮬레이션을 수행하고 전체 시뮬레이션 수행 시간을 측정하고 비교해보았다. 성능 평가 결과를 통해서 DDS를 사용하는 시뮬레이션 수행 속도가 HLA/RTI를 사용하는 것에 비해 최소 1.14배 이상 빠른 것을 확인할 수 있었다.