• Journal of KIISE:Computing Practices and Letters
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• v.6 no.2
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• pp.113-119
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• 2000

In this paper, we design and implement a query processor of real-time main memory database systems, which reflect the characteristics of main memory database systems and satisfy timing constraints. The proposed query processor manages real-time data that has timing constraint by exploiting meta database. It supports CLI in order to make application programs. It also supports extended CLI and stored CLI. The former can be expressed the Information on real-time transaction. The latter is designed to support frequently processed transaction. The proposed query processor is implemented as query processor of real-time database management systems. We Present performance evaluation results that illustrate ratio of transaction, which satisfy deadline are increased by the query processing ability of system and the efficient management of real-time data.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.3
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1032-1036
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• 1990

This paper describes a system which enables a real-time measurement of 2-D water flow field. One distinctive feature of our system is that velocity vectors of water flow are obtained from the movement of tracer particles at video rate. In order to enable a fast measurement a real time video processor and two Digital Signal Processor(TMS32OC25) are employed. The real-time video processor extracts contours of tracer particles in order to reduce the amount of image data to be processed. And two DSP(Digital Signal Processor) analyse the correlation of every tracer paticle in the consecutive two images to obtain the velocity distribution of water flow.

• International journal of advanced smart convergence
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• v.8 no.1
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• pp.9-17
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• 2019

In this article, we present a performance enhancement scheme for mobile applications by adopting persistent memory. The proposed scheme supports the deadline guarantee of real-time applications like a video player, and also provides reasonable performances for non-real-time applications. To do so, we analyze the program execution path of mobile software platforms and find two sources of unpredictable time delays that make the deadline-guarantee of real-time applications difficult. The first is the irregular activation of garbage collection in flash storage and the second is the blocking and time-slice based scheduling used in mobile platforms. We resolve these two issues by adopting high performance persistent memory as the storage of real-time applications. By maintaining real-time applications and their data in persistent memory, I/O latency can become predictable because persistent memory does not need garbage collection. Also, we present a new scheduler that exclusively allocates a processor core to a real-time application. Although processor cycles can be wasted while a real-time application performs I/O, we depict that the processor utilization is not degraded significantly due to the acceleration of I/O by adopting persistent memory. Simulation experiments show that the proposed scheme improves the deadline misses of real-time applications by 90% in comparison with the legacy I/O scheme used in mobile systems.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.7
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.6
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• pp.626-631
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• 1997

This paper represents the design of a real-time image preprocessing system. The preprocessing system performs hardware-wise mask operations and thresholding operations at the speed of camera output single rate. The preprocessing system consists of the preprocessing board and the main processing board. The preprocessing board includes preprocessing unit that includes a $5\times5$ mask processor and LUT, and can perform mask and threshold operations in real-time. To achieve high-resolution image input data($20485\timesn$), the preprocessing board has a linescan camera interface. The main processing board includes the image processor unit and main processor unit. The image processor unit is equipped with TI's TMS320C32 DSP and can perform image processing algorithms at high speed. The main processor unit controls the operation of total system. The proposed system is faster than the conventional CPU based system.

• Current Optics and Photonics
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• v.2 no.5
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• pp.453-459
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• 2018

We have developed a high-performance signal-processing and image-rendering heterogeneous computation system for optical coherence tomography (OCT) on mobile processor. In this paper, we reveal it by demonstrating real-time OCT image processing using a Snapdragon 800 mobile processor, with the introduction of a heterogeneous image visualization architecture (HIVA) to accelerate the signal-processing and image-visualization procedures. HIVA has been designed to maximize the computational performances of a mobile processor by using a native language compiler, which targets mobile processor, to directly access mobile-processor computing resources and the open computing language (OpenCL) for heterogeneous computation. The developed mobile image processing platform requires only 25 ms to produce an OCT image from $512{\times}1024$ OCT data. This is 617 times faster than the naïve approach without HIVA, which requires more than 15 s. The developed platform can produce 40 OCT images per second, to facilitate real-time mobile OCT image visualization. We believe this study would facilitate the development of portable diagnostic image visualization with medical imaging modality, which requires computationally expensive procedures, using a mobile processor.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.8
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• pp.1217-1226
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• 1989

This paper describes a design of hardware system for real time automatic diagnosis of ECG arrhythmia based on pipeline processor consisting of three microcomputer. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters-heart rate, morpholigy, axis, and ST segment-are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. Therefore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory unit is designed to decrease the delay time caused by data transfer between processors and be which the delay time can be taken 1% of one clock period.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.731-733
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• 1988

This paper describes a design of hardware system for real time automatic diagnosis of ECG arrhythmia based on pipeline processor consisting of the three microcomputer. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters - heart rate, morphology, axis, and ST segment - are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. There-fore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and by which the delay time can be taken 1 % of one clock period.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.1107-1111
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• 2005

The DVR system realization with watermarking and MPEG-4 for real time processing speed improvement is presented in this paper. For the real time processing the system is used the DSP processor, Quick DMA for data transmission, watermarking for security and MPEG-4 compression for facility. The algorithms are that the operational structure has the internal memory of processor, and the optimal realization is suitable to form the DSP processor structure r processed for the iterative operations. The experimental result shows the real time processing is improved 12% over for the D1 image in comparison with the other system.