• Korean Journal of Materials Research
• /
• v.22 no.4
• /
• pp.202-206
• /
• 2012

$CoSi_2$ was formed through annealing of atomic layer deposition Co thin films. Co ALD was carried out using bis(N,N'-diisopropylacetamidinato) cobalt ($Co(iPr-AMD)_2$) as a precursor and $NH_3$ as a reactant; this reaction produced a highly conformal Co film with low resistivity ($50\;{\mu}{\Omega}cm$). To prevent oxygen contamination, $ex-situ$ sputtered Ti and $in-situ$ ALD Ru were used as capping layers, and the silicide formation prepared by rapid thermal annealing (RTA) was used for comparison. Ru ALD was carried out with (Dimethylcyclopendienyl)(Ethylcyclopentadienyl) Ruthenium ((DMPD)(EtCp)Ru) and $O_2$ as a precursor and reactant, respectively; the resulting material has good conformality of as much as 90% in structure of high aspect ratio. X-ray diffraction showed that $CoSi_2$ was in a poly-crystalline state and formed at over $800^{\circ}C$ of annealing temperature for both cases. To investigate the as-deposited and annealed sample with each capping layer, high resolution scanning transmission electron microscopy (STEM) was employed with electron energy loss spectroscopy (EELS). After annealing, in the case of the Ti capping layer, $CoSi_2$ about 40 nm thick was formed while the $SiO_x$ interlayer, which is the native oxide, became thinner due to oxygen scavenging property of Ti. Although Si diffusion toward the outside occurred in the Ru capping layer case, and the Ru layer was not as good as the sputtered Ti layer, in terms of the lack of scavenging oxygen, the Ru layer prepared by the ALD process, with high conformality, acted as a capping layer, resulting in the prevention of oxidation and the formation of $CoSi_2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.80-80
• /
• 2009

Recently, multiferroics have attracted much attention due to their numorous potentials. In this work, we attemped to utilize the multiferroics as an alternative material for ferroelectrics. Ferroelectric materials have been stadied to ferroelectric random access memories, however, some inevitable problems prevent it from inplementation. multiferroics shows a ferroelectricity and has low process temperature $BiFeO_3$(BFO) films have good ferroelectric properties but poor leakage characterization. Thus we tried, in this work, to adopt $HfO_2$ insulating layer for metal-ferroelectric-insulator-semiconductor(MFMIS) structure to surpress to leakage current. $BiFeO_3$(BFO) thin films were fabricared by using a sol-gel method on $HfO_2/Si$ structure. Ferroelectric BFO films on a p-type Si(100)wafer with a $HfO_2$ buffer layer have been fabricated to form a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The $HfO_2$ insulator were deposited by using a sol-gel method. Then, they were carried out a rapid thermal annealing(RTA) furnace at $750\;^{\circ}C$ for 10 min in $N_2$. BFO films on the $HfO_2/Si$ structures were deposited by sol-gel method and they were crystallized rapid thermal annealing in $N_2$ atomsphere at $550\;^{\circ}C$ for 5 min. They were characterized by atomic force microscopy(AFM) and Capacitance-voltage(C-V) curve.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.8 no.6
• /
• pp.37-47
• /
• 1998

This paper proposes a controller design method using the evolutionary computation algorithm and the fuzzy logic to control the wafer temperature in rapid thermal processing. First, we design the feedforward static controller to provide the control powers of the lamps for the given steady state temperature. Second, the feedforward dynamic controller is designed for the additional control powers to achieve a given transient response. These feedforward controllers are implemented by using the fuzzy logic to act as a global nonlinear controller over a wide range of operating points. The parameters of these controllers are optimized by using the evolutionary computation algorithm so that it can be used when the mathematical model is not available. In addition, the feedback error controller is introduced to compensate the feedforward controllers when there exist disturbances and modeling errors. The gain of feedback error controller is also obtained by the evolutionary computation algorithm. Through simulations, we verify the proposed control system can give a satisfactory performance.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.652-652
• /
• 2013

The conventional thermal chemical vapor deposition (CVD) setup for the graphene synthesis has mainly used convective heat transfer in order to heat a catalyst (e.g. Cu) up to $1,000^{\circ}C$. Although the conventional CVD has been so far widely accepted as the most appropriate candidate enabling mass-production of high-quality graphene, this method has stillremained under the standard for the commercialization largely due to the poor productivity arisen out of the required long processing time. Here, we introduced a fast and efficient synthetic route toward CVD-graphene. Unlike the conventional CVD using convection heat transfer, we adopted a CVD setup utilizing conduction heat transfer between Cu catalyst and rapid heating source. The high thermal conductive nature of Cu and the employed rapid heating source led to the remarkable reduction in processing timeas compared to the conventional convection based CVD (Fig. 1A), moreover, the synthesized graphene was turned out to have comparable quality to that synthesized by the conventional CVD (Fig. 1B). For the optimization of the conduction based CVD process, the parametric studies were thoroughly performed using through Raman spectroscopy and electrical sheet resistance measurement. Our approach is thought to be worth considerable in order to enhance productivity of the CVD graphene in the industry.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.6
• /
• pp.55-65
• /
• 1998

In industrial fields, RTP(rapid thermal processing) system is widely used for improving the oxidation and the annealing in semiconductor manufacturing process. The main control factors are temperature control of wafer and uniformity in the wafer. In this paper, we propose an $H^{\infty}$ controller design of RTP system satisfying robust stability and performance using weighted mixed sensitivity miniimization and loop shaping technique. And we need reduction technique because of the difficulty of implementation with the obtained high order controller for original model and reduced models, namely, Hankel, square-root balanced, and Schur balanced methods. An example is proposed to show the validity of the proposed method.

• Journal of the Korean Vacuum Society
• /
• v.6 no.1
• /
• pp.28-35
• /
• 1997

Effects of rapid thermal annealing on the characteristics of Cu films deposited from the (hfac)Cu(VTMS) precursor and on the barrier properties of TiN layers were studied. By the post-annealing, the electrical characteristics of Cu/TiN and the microstructures of Cu films were significantly changed. The properties of Cu films were more sensitive to the annealing temperature than the annealing time. Sheet resistance started to increase above $400^{\circ}C$, and the interreaction between Cu and Ti and the oxidation of Cu layer were observed above $600^{\circ}C$. The grain growth of Cu with the (111) preferred orientation was found to be most pronounced at $500^{\circ}C$. It revealed that the optimum annealing conditions for MOCVD-Cu/PVD-TiN structures to enhance the electrical characteristics without degradation of TiN barriers were in the range of $400^{\circ}C$.

• Journal of the Korean Vacuum Society
• /
• v.17 no.2
• /
• pp.156-159
• /
• 2008

The electrical characteristic of SiGe-on-SOI (SGOI) wafer with different Ge concentration were evaluated by pseudo-MOSFET. Epitaxial SiGe layers was grown directly on top of SOI with Ge concentrations of 16.2, 29.7, 34.3 and 56.5 at.%. As Ge concentration increased, leakage current increased and threshold voltage shifted from 3 V to 7 V in nMOSFET, from -7 V to -6 V in pMOSFET. The interface states between buried oxide and top of Si was significantly increased by the rapid thermal annealing (RTA) process, and so the electrical characteristic of SGOI wafer degraded. On the other hand, additional post RTA　annealing (PRA) showed that it was effective in decreasing the interface states generated by RTA processes and the electrical characteristic of SGOI wafer enhanced higher than initial state.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.22 no.2
• /
• pp.26-32
• /
• 2021

The photovoltaic properties and microstructure changes were observed while perovskite solar cells (PSCs) with a fabricated carbon electrode were formed using the following annealing processes: hot-plate, oven, and rapid thermal annealing (RTA). Perovskite solar cells with a glass/FTO/compact TiO2/meso TiO2/meso ZrO2/carbon structure were prepared. The photovoltaic properties and microstructure changes in the PSCs were analyzed using a solar simulator, optical microscopy, and field emission scanning electron microscopy. An analysis of the photovoltaic properties revealed outstanding properties when RTA was applied to the cells. Microstructure analysis showed that perovskite was formed locally on the carbon electrode surface when hot-plate and oven annealing were applied. On the other hand, PSC with RTA showed a flat surface without extra perovskite agglomeration. Denser perovskite formed on the porous carbon electrode layer with RTA showed superior photovoltaic properties. These results suggest that the RTA process might be appropriate for the massive production of carbon electrode PSCs considering the processing time.

• Korean Journal of Materials Research
• /
• v.31 no.11
• /
• pp.619-625
• /
• 2021

Cu₂ZnSn(S,Se)₄ (CZTSSe) based thin-film solar cells have attracted growing attention because of their earth-abundant and non-toxic elements. However, because of their large open-circuit voltage (V_oc)-deficit, CZTSSe solar cells exhibit poor device performance compared to well-established Cu(In,Ga)(S,Se)₂ (CIGS) and CdTe based solar cells. One of the main causes of this large V_oc-deficit is poor absorber properties for example, high band tailing properties, defects, secondary phases, carrier recombination, etc. In particular, the fabrication of absorbers using physical methods results in poor surface morphology, such as pin-holes and voids. To overcome this problem and form large and homogeneous CZTSSe grains, CZTSSe based absorber layers are prepared by a sputtering technique with different RTA conditions. The temperature is varied from 510 ℃ to 540 ℃ during the rapid thermal annealing (RTA) process. Further, CZTSSe thin films are examined with X-ray diffraction, X-ray fluorescence, Raman spectroscopy, IPCE, Energy dispersive spectroscopy and Scanning electron microscopy techniques. The present work shows that Cu-based secondary phase formation can be suppressed in the CZTSSe absorber layer at an optimum RTA condition.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.5
• /
• pp.329-337
• /
• 2001

It has been known that the leakage current in the low field region consists of the dielectric relaxation current and intrinsic leakage current, which cause the charge loss in dynamic random access memory (DRAM) storage capacitor using (Ba,Sr)TiO$_{3}$ (BST) thin film. Especially, the dielectric relaxation current should be seriously considered since its magnitude is much larger than that of the intrinsic leakage current in giga-bit DRAM operation voltage (~IY). In this study, thermally stimulated current (TSC) measurement was at first applied to investigate the activation energy of traps and relative evaluation of the density of traps according to process change. And, through comparing TSC to early methods of I-V or I-t measurement and analyzing, we identify the origin of the dielectric relaxation current and investigate the reliability of TSC measurement. First, the polarization condition such as electric field, time, temperature and heating rate was investigated for reliable TSC measurement. From the TSC measurement, the energy level of traps in the BST thin film has been investigated and evaluated to be 0.20($\pm$0.01) eV and 0.45($\pm$0.02) eV. Based on the TSC measurement results before and after rapid thermal annealing (RTA) process, oxygen vacancy is concluded to be the origin of the traps. TSC characteristics with thermal annealing in the MIM BST capacitor have shown the same trends with the current-voltage (I-V) and current-time (I-t) characteristics. This means that the TSC measurement is one of the effective methods to characterize the traps in the BST thin film.