• Korean Journal of Materials Research
• /
• v.12 no.11
• /
• pp.883-888
• /
• 2002

We investigated the void formation in composite-titanium silicide($TiSi_2$) process. We varied the process conditions of polycrystalline/amorphous silicon substrate, composite $TiSi_2$ deposition temperature, and silicidation annealing temperature. We report that the main reason for void formation is the mass transport flux discrepancy of amorphous silicon substrate and titanium in composite layer. Sheet resistance in composite $TiSi_2$ without patterns is mainly affected by silicidation rapid thermal annealing (RTA) temperature. In addition, sheet resistance does not depend on the void defect density. Sheet resistance with sub-0.5 $\mu\textrm{m}$ patterns increase abnormally above $850^{\circ}C$ due to agglomeration. Our results imply that $sub-750^{\circ}C$ annealing is appropriate for sub 0.5 $\mu\textrm{m}$ composite X$sub-750_2$ process.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.266-269
• /
• 2000

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance and leakage tungsten bit-line process with various RTP(Rapid Thermal Process) temperature. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF2 ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1994.11a
• /
• pp.54-58
• /
• 1994

H$_2$ bake and GeH$_4$ clean are used as a in-situ pre-clean method in low temperature Si based epitaxial growth technology using rapid thermal processing chemical vapor deposition (RTPCVD). In this paper, the H$_2$ bake and GeH$_4$ clean processes are optimized for low surface defect density using Taguchi method. In H$_2$ bake process, the epitaxial growth temperature affects dominantly on the surface defect density, and the next affecting factors are H$_2$ bake temperature and rinse time in de-ionised water. In GeH$_4$ clean process, GeH$_4$ clean temperature affects most strongly on the surface defect density, and the minor factor is GeH$_4$flow rate. The optimum process conditions predicted fly Taguchi method agree well with tile experimental data in both in-situ clean processes.

• Journal of the Korean institute of surface engineering
• /
• v.35 no.6
• /
• pp.377-382
• /
• 2002

We investigated the appropriate wet cleaning process for Co-Ti-Si compounds formed on top of cobalt disilicide made from Co/Ti deposition and two rapid thermal annealing (RTA). We employed three wet cleaning processes, WP1 ($H_2$SO$_4$ etchant), WP2 ($NH_4$OH etchant), and WP3 which execute sequentially WP1 and WP2 after the first RTA. All samples were cleaned with BOE etchant after the second RTA. We characterized the sheet resistance with process steps by a four-point probe, the microstructure evolution by a cross detail sectional transmission electron microscope, a Auger depth profiler, and a X-ray diffractometer (XRD). We confirmed WP3 wet cleaning process were the most suitable to remove CoTiSi layer selectively.

• Proceedings of the Korean Society for Technology of Plasticity Conference
• /
• 2007.05a
• /
• pp.199-204
• /
• 2007

Hot embossing, one of Nanoimprint Lithography(NIL) techniques, has been getting attention as an alternative candidate of next generation patterning technologies by the advantages of simplicity and low cost compared to conventional photolithographies. A typical hot embossing usually, however, takes more than ten minutes for one cycle of the process because of a long thermal cycling. Over the last few years a number of studies have been made to reduce the cycle time for hot embossing or similar patterning processes. The target of this research is to develop an induction heating apparatus for heating a metallic micro patterning mold at very high speed with the large-area uniformity of temperature distribution. It was found that a 0.5 mm-thick nickel mold can be heated from $25^{\circ}C$ to $150^{\circ}C$ within 1.5 seconds with the temperature variation of ${\pm}5^{\circ}C$ in 4-inch diameter area, using the induction heating apparatus.

• Journal of the Korean Ceramic Society
• /
• v.27 no.2
• /
• pp.249-255
• /
• 1990

High Tc Supperconducting thin films were fabricated by rf magnetron sputtering method. We have successfully controlled the compositions of films by adding sintered CuO pellets on YBa2Cu3O7-x single target. High Tc thin films with large grian size and good crystal habit were obtained by rapid thermal annealing process. The films deposited on SrTiO3(100) single crystal substrate indicated the existence of c-axis prefered orientation confirmed by XRD and SEM analysis. The Tc, zero's of sharp resistive transition for rapid annealed films deposited on polycrystalline YSZ substrate and on SrTiO3(100) single crystal substrate were 79K and 88K, respectively.

• Korean Journal of Materials Research
• /
• v.17 no.2
• /
• pp.73-80
• /
• 2007

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.

• Journal of Sensor Science and Technology
• /
• v.27 no.1
• /
• pp.40-46
• /
• 2018

In this paper, we focus on optimization of a boron ($^{11}B$)-implanted n type Si epi substrate for obtaining near-zero temperature coefficient of resistance (TCR) at temperature range from 25 to $125^{\circ}C$. The $^{11}B$-implantation on the N type-Si epi substrate formed isolation from the rest of the N-type Si by the depletion region of a PN junction. The TCR increased as the temperature of rapid thermal anneal (RTA) was increased at the temperature range from $900^{\circ}C$ to $1000^{\circ}C$ for the $p^+$ contact with implantation at dose of $1E16/cm^2$, but sheet resistance of this film was decreased. After the optimization of anneal process condition, the TCR of $1126.7{\pm}30.3$ (ppm/K) was obtained for the $p^-$ resistor-COB package chips contained $p^+$ contact with the implantation of $5E14/cm^2$. This shows the potential of the $^{11}B$-implanted n type Si epi substrate as a resistor for pressure sensor in thermal stable environment applications..

• Korean Journal of Materials Research
• /
• v.16 no.10
• /
• pp.656-662
• /
• 2006

We fabricated thermal evaporated 10 nm-$Ni_xCo_{1-x}$ (x=0.2, 0.5 and 0.8) /(poly)Si films to form nanothick cobalt nickel composite silicides by a rapid thermal annealing at $700{\sim}1100^{\circ}C$ for 40 seconds. A field emission scanning electron microscope and a micro-Raman spectrometer were employed for microstructure and silicon residual stress characterization, respectively. We observed self-aligned micro-pinholes on single crystal silicon substrates silicidized at $1100^{\circ}C$. Raman silicon peak shift indicates that the residual tensile strain of $10^{-3}$ in single crystal silicon substrates existed after the silicide process. We propose thermal stress from silicide exothermic reaction and high temperature silicidation annealing may cause the pinholes. Those pinholes are expected to be avoided by lowering the silicidation temperature. Our results imply that we may use our newly proposed composite silicides to induce the appropriate strained layer in silicion substrates.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.7 no.3
• /
• pp.332-337
• /
• 2006

We prepared 100 nm-thick CoNi composite silicide on a 70 nm-thick polysilicon substrate. Composite silicide laye.s were formed by rapid thermal annealing(RTA) at the temperatures of $700^{\circ}C,\;900^{\circ}C,\;1000^{\circ}C$ for 40 seconds. A Focused ion beam (FIB) was used to make nano-patterns with the operation range of 30 kV and $1{\sim}100$ pA. We investigated the change of thickness, line width, and the slope angle of the silicide patterns by FIB. More easily made with the FIB process than with the conventional polycide process. We successfully fabricated sub-100nm etched patterns with FIB condition of 30kv-30pA. Our result implies that we may integrate nano patterns with our newly proposed CoNi composite silicides.