• Asian-Australasian Journal of Animal Sciences
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• v.29 no.12
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• pp.1682-1687
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• 2016

The objective of this study was to estimate the genetic parameters of milk protein yields in Iranian Holstein dairy cattle. A total of 1,112,082 test-day milk protein yield records of 167,269 first lactation Holstein cows, calved from 1990 to 2010, were analyzed. Estimates of the variance components, heritability, and genetic correlations for milk protein yields were obtained using a random regression test-day model. Milking times, herd, age of recording, year, and month of recording were included as fixed effects in the model. Additive genetic and permanent environmental random effects for the lactation curve were taken into account by applying orthogonal Legendre polynomials of the fourth order in the model. The lowest and highest additive genetic variances were estimated at the beginning and end of lactation, respectively. Permanent environmental variance was higher at both extremes. Residual variance was lowest at the middle of the lactation and contrarily, heritability increased during this period. Maximum heritability was found during the 12th lactation stage ($0.213{\pm}0.007$). Genetic, permanent, and phenotypic correlations among test-days decreased as the interval between consecutive test-days increased. A relatively large data set was used in this study; therefore, the estimated (co)variance components for random regression coefficients could be used for national genetic evaluation of dairy cattle in Iran.

• Journal of the Korean Data and Information Science Society
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• v.9 no.2
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• pp.237-246
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• 1998

We put the pseudo-random number generator into catagories like MiCG, MuCG, URG, ICG, EICG, and test uniformity and independency by 10,000 times through n empirical trial after selecting this random number generator. Here, from a fraction of data(20, 40, 60, 80, 100) with a significance level of 0.1, 0.05 and 0.01, we drive cumulative frequency with K-S, $X^{2}$, poker, run, autocorrelation test. As a result from the uniformity and independency among five random number generators based on all these data, all random number generator except EICG passed uniformity and independency test, and the URG turn out to be excellent in periodicity.

• Journal of the Korean Data and Information Science Society
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• v.14 no.4
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• pp.951-963
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• 2003

In this paper, we propose goodness of fit test statistics based on the estimated Kullback-Leibler information functions using the data from three step stress accelerated life test. This acceleration model is assumed to be a tampered random variable model. The power of the proposed test under various alternatives is compared with Kolmogorov-Smirnov statistic, Cramer-von Mises statistic and Anderson-Darling statistic.

• Journal of Korean Society for Quality Management
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• v.25 no.3
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• pp.11-21
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• 1997

The mean residual life(MRL) function gives the expected remaining life of a item at age t. In particular F is said to be an increasing intially then decreasing MRL(IDMRL) distribution if there exists a turing point $t^*\ge0$ such that m(s)$\le$ m(t) for 0$$\le s$\le$ t $t^*$, m(s)$\ge$ m(t) for $t^*\le$ s$\le$ t. If the preceding inequality is reversed, F is said to be a decreasing initially then increasing MRL(DIMRL) distribution. Hawkins, et al.(1992) proposed test of H0 : F is exponential versus$H_1$: F is IDMRL, and $H_0$ versus $H_1$' : F is DIMRL when turning point is unknown. Their test is based on a complete random sample $X_1$, …, $X_n$ from F. In this paper, we generalized Hawkins-Kochar-Loader test to random censored data.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.5
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• pp.699-708
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• 1990

This paper proposes two test procedures for detecting functional faults in semiconductor random access memories (RAM's) and a new testimg scheme to execute the proposed test procedures. The first test procedure detects stuck-at faults, coupling faults and decoder faults, and requires 19N operations, which is an improvement over conventional procedures. The second detects restricted patternsensitive faults and requires 69N operations. The proposed scheme uses Built-In Self Testing (BIST) techniques. The scheme can write into more memory cells than I/O pins can in a write cycle in test mode. By using the scheme, the number of write operations is reduced and then much testing time is saved.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• KIPS Transactions on Software and Data Engineering
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• v.2 no.12
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• pp.829-840
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• 2013

This paper proposes a modified RRT (Rapidly exploring Random Tree) algorithm utilizing a heuristic input analysis and suggests a test case generation method from Simulink/Stateflow model using the proposed RRT algorithm. Though the typical RRT algorithm is an efficient method to solve the reachability problem to definitely be resolved for generating test cases of model in a black box manner, it has a drawback, an inefficiency of test case generation that comes from generating random inputs without considering the internal states and the test targets of model. The proposed test case generation method increases efficiency of test case generation by analyzing the test targets to be satisfied at the current state and heuristically deciding the inputs of model based on the analysis during expanding an RRT, while maintaining the merit of RRT algorithm. The proposed method is evaluated with the models of ECUs embedded in a commercial passenger's car. The performance is compared with that of the typical RRT algorithm.

• The KIPS Transactions:PartD
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• v.10D no.3
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• pp.541-546
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• 2003

We present a random bit generator that uses fingerprint image as the source of random, and the random bit generator is the first generator in the world that uses biometric information for the source of random in the world. The generator produces, on the average, 9,334 bits a fingerprint image in 0.03 second, and the produced bit sequence passes all 16 statistical tests that are recommended by NIST for testing the randomness.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.184-193
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• 2015

This paper proposes a cost-efficient and automatic method for large data acquisition from a test chip without expensive equipment to characterize random process variation in an integrated circuit. Our method requires only a test chip, a personal computer, a cheap digital-to-analog converter, a controller and multimeters, and thus large volume measurement can be performed on an office desk at low cost. To demonstrate the proposed method, we designed a test chip with a current model logic driver and an array of 128 current mirrors that mimic the random process variation of the driver's tail current mirror. Using our method, we characterized the random process variation of the driver's voltage due to the random process variation on the driver's tail current mirror from large volume measurement data. The statistical characteristics of the driver's output voltage calculated from the measured data are compared with Monte Carlo simulation. The difference between the measured and the simulated averages and standard deviations are less than 20% showing that we can easily characterize the random process variation at low cost by using our cost-efficient automatic large data acquisition method.

• Journal of IKEEE
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• v.24 no.1
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• pp.52-58
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• 2020

This paper describes a hardware implementation of a true random number generator (TRNG) for information security applications. A new approach for TRNG design was proposed by adopting random transition rules in cellular automata and applying different transition rules at every time step. The TRNG circuit was implemented on Spartan-6 FPGA device, and its hardware operation generating random data with 100 MHz clock frequency was verified. For the random data of 2×10⁷ bits extracted from the TRNG circuit implemented in FPGA device, the randomness characteristics of the generated random data was evaluated by the NIST SP 800-22 test suite, and all of the fifteen test items were found to meet the criteria. The TRNG in this paper was implemented with 139 slices of Spartan-6 FPGA device, and it offers 600 Mbps of the true random number generation with 100 MHz clock frequency.