• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.642-642
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• 2013

Graphene, two dimensional single layer of carbon atoms, has tremendous attention due to its superior property such as high electron mobility, high thermal conductivity and optical transparency. Especially, chemical vapor deposition (CVD) grown graphene has been used as a promising material for high quality and large-scale graphene film. Unfortunately, although CVD-grown graphene has strong advantages, application of the CVD-grown graphene is limited due to ineffective transfer process that delivers the graphene onto a desired substrate by using polymer support layer such as PMMA(polymethyl methacrylate). The transferred CVD-grown graphene has serious drawback due to remaining polymeric residues generated during transfer process, which induces the poor physical and electrical characteristics by a p-doping effect and impurity scattering. To solve such issue incurred during polymer transfer process of CVD-grown graphene, various approaches including thermal annealing, chemical cleaning, mechanical cleaning have been tried but were not successful in getting rid of polymeric residues. On the other hand, lithographical patterning of graphene is an essential step in any form of microelectronic processing and most of conventional lithographic techniques employ photoresist for the definition of graphene patterns on substrates. But, application of photoresist is undesirable because of the presence of residual polymers that contaminate the graphene surface consistent with the effects generated during transfer process. Therefore, in order to fully utilize the excellent properties of CVD-grown graphene, new approach of transfer and patterning techniques which can avoid polymeric residue problem needs to be developed. In this work, we carried out transfer and patterning process simultaneously with no polymeric residue by using a metal etch mask. The patterned thin gold layer was deposited on CVD-grown graphene instead of photoresists in order to make much cleaner and smoother surface and then transferred onto a desired substrate with PMMA, which does not directly contact with graphene surface. We compare the surface properties and patterning morphology of graphene by scanning electron microscopy (SEM), atomic force microscopy(AFM) and Raman spectroscopy. Comparison with the effect of residual polymer and metal on performance of graphene FET will be discussed.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.254-255
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• 2012

Interest in nano-crystalline silicon (nc-Si) thin films has been growing because of their favorable processing conditions for certain electronic devices. In particular, there has been an increase in the use of nc-Si thin films in photovoltaics for large solar cell panels and in thin film transistors for large flat panel displays. One of the most important material properties for these device applications is the macroscopic charge-carrier mobility. Hydrogenated amorphous silicon (a-Si:H) or nc-Si is a basic material in thin film transistors (TFTs). However, a-Si:H based devices have low carrier mobility and bias instability due to their metastable properties. The large number of trap sites and incomplete hydrogen passivation of a-Si:H film produce limited carrier transport. The basic electrical properties, including the carrier mobility and stability, of nc-Si TFTs might be superior to those of a-Si:H thin film. However, typical nc-Si thin films tend to have mobilities similar to a-Si films, although changes in the processing conditions can enhance the mobility. In polycrystalline silicon (poly-Si) thin films, the performance of the devices is strongly influenced by the boundaries between neighboring crystalline grains. These grain boundaries limit the conductance of macroscopic regions comprised of multiple grains. In much of the work on poly-Si thin films, it was shown that the performance of TFTs was largely determined by the number and location of the grain boundaries within the channel. Hence, efforts were made to reduce the total number of grain boundaries by increasing the average grain size. However, even a small number of grain boundaries can significantly reduce the macroscopic charge carrier mobility. The nano-crystalline or polymorphous-Si development for TFT and solar cells have been employed to compensate for disadvantage inherent to a-Si and micro-crystalline silicon (${\mu}$-Si). Recently, a novel process for deposition of nano-crystralline silicon (nc-Si) thin films at room temperature was developed using neutral beam assisted chemical vapor deposition (NBaCVD) with a neutral particle beam (NPB) source, which controls the energy of incident neutral particles in the range of 1~300 eV in order to enhance the atomic activation and crystalline of thin films at room temperature. In previous our experiments, we verified favorable properties of nc-Si thin films for certain electronic devices. During the formation of the nc-Si thin films by the NBaCVD with various process conditions, NPB energy directly controlled by the reflector bias and effectively increased crystal fraction (~80%) by uniformly distributed nc grains with 3~10 nm size. The more resent work on nc-Si thin film transistors (TFT) was done. We identified the performance of nc-Si TFT active channeal layers. The dependence of the performance of nc-Si TFT on the primary process parameters is explored. Raman, FT-IR and transmission electron microscope (TEM) were used to study the microstructures and the crystalline volume fraction of nc-Si films. The electric properties were investigated on Cr/SiO2/nc-Si metal-oxide-semiconductor (MOS) capacitors.

• 한국신재생에너지학회:학술대회논문집
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• 2005.11a
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• pp.561-566
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• 2005

Polycrystalline silicon films were deposited using hot wire CVD (HWCVD). The deposition of silicon thin films was approached by the theory of charged clusters (TCC). The TCC states that thin films grow by self-assembly of charged clusters or nanoparticles that have nucleated in the gas phase during the normal thin film process. Negatively charged clusters of a few nanometer in size were captured on a transmission electron microscopy (TEM) grid and observed by TEM. The negatively charged clusters are believed to have been generated by ion-induced nucleation on negative ions, which are produced by negative surface ionization on a tungsten hot wire. The electric current on the substrate carried by the negatively charged clusters during deposition was measured to be approximately $-2{\mu}A/cm^2$. Silicon thin films were deposited at different $SiH_4$ and $H_2$ gas mixtures and filament temperatures. The crystalline volume fraction, grain size and the growth rate of the films were measured by Raman spectroscopy, X-ray diffraction and scanning electron microscopy. The deposit ion behavior of the si1icon thin films was related to properties of the charged clusters, which were in turn controlled by the process conditions. In order to verify the effect of the charged clusters on the growth behavior, three different electric biases of -200 V, 0 V and +25 V were applied to the substrate during the process, The deposition rate at an applied bias of +25 V was greater than that at 0 V and -200 V, which means that the si1icon film deposition was the result of the deposit ion of charged clusters generated in the gas phase. The working pressures had a large effect on the growth rate dependency on the bias appled to the substrate, which indicates that pressure affects the charging ratio of neutral to negatively charged clusters. These results suggest that polycrystalline silicon thin films with high crystalline volume fraction and large grain size can be produced by control1ing the behavior of the charged clusters generated in the gas phase of a normal HWCVD reactor.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.1
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• pp.25-32
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• 2007

We investigated the silicide reaction stability between 10 nm-Col-xNix alloy films and silicon substrates with the existence of 4 nm-thick natural oxide layers. We thermally evaporated 10 nm-Col-xNix alloy films by varying $x=0.1{\sim}0.9$ on naturally oxidized single crystal and 70 nm-thick polycrystalline silicon substrates. The films structures were annealed by rapid thermal annealing (RTA) from $600^{\circ}C$ to $1100^{\circ}C$ for 40 seconds with the purpose of silicidation. After the removal of residual metallic residue with sulfuric acid, the sheet resistance, microstructure, composition, and surface roughness were investigated using a four-point probe, a field emission scanning electron microscope, a field ion bean4 an X-ray diffractometer, and an Auger electron depth profiling spectroscope, respectively, to confirm the silicide reaction. The residual stress of silicon substrate was also analyzed using a micro-Raman spectrometer We report that the silicide reaction does not occur if natural oxides are present. Metallic oxide residues may be present on a polysilicon substrate at high silicidation temperatures. Huge residual stress is possible on a single crystal silicon substrate at high temperature, and these may result in micro-pinholes. Our results imply that the natural oxide layer removal process is of importance to ensure the successful completion of the silicide process with CoNi alloy films.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.376-376
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• 2012

Semiconductor nanowires (NWs) are future building block for nano-scale devices. Especially, Ge NWs are fascinated material due to the high electrical conductivity with high carrier mobility. It is strong candidate material for post-CMOS technology. However, thermal stability of Ge NWs are poor than conventional semiconductor material such as Si. Especially, when it reduced size as small as nano-scale it will be melted around CMOS process temperature due to the melting point depression. Recently, Graphene have been intensively interested since it has high carrier mobility with single atomic thickness. In addition, it is chemically very stable due to the $sp^2$ hybridization. Graphene films shows good protecting layer for oxidation resistance and corrosion resistance of metal surface using its chemical properties. Recently, we successfully demonstrated CVD growth of monolayer graphene using Ge catalyst. Using our growth method, we synthesized Ge/graphene core/shell (Ge@G) NW and conducted it for highly thermal stability required devices. We confirm the existence of graphene shell and morphology of NWs using SEM, TEM and Raman spectra. SEM and TEM images clearly show very thin graphene shell. We annealed NWs in vacuum at high temperature. Our results indicated that surface melting phenomena of Ge NWs due to the high surface energy from curvature of NWs start around $550^{\circ}C$ which is $270^{\circ}C$ lower than bulk melting point. When we increases annealing temperature, tip of Ge NWs start to make sphere shape in order to reduce its surface energy. On the contrary, Ge@G NWs prevent surface melting of Ge NWs and no Ge spheres generated. Furthermore, we fabricated filed emission devices using pure Ge NWs and Ge@G NWs. Compare with pure Ge NWs, graphene protected Ge NWs show enhancement of reliability. This growth approach serves a thermal stability enhancement of semiconductor NWs.

• Carbon letters
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• v.24
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• pp.97-102
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• 2017

Graphite fibers are materials with a high specific modulus that have attracted much interest in the aerospace industry, but their high manufacturing cost and low yield are still problems that prevent their wide applications in practice. This paper presents a laser-based process for graphitization of carbon fiber (CF) and explores the effect of laser radiation on the microstructure of CF. The obtained Raman spectra indicate that the outer surface of CF evolves from turbostratic structures into a three-dimensional ordered state after being irradiated by a laser. The X-ray diffraction data revealed that the growth of crystallite was parallel to the fiber axis, and the interlayer spacing $d_{002}$ decreased from 0.353 to 0.345 nm. The results of scanning electron microscopy revealed that the surface of irradiated CFs was rougher than that of the unirradiated ones and there were scale-like small fragments that had peeled off from the fibers. The tensile modulus increased by 17.51% and the Weibull average tensile strength decreased by 30.53% after being irradiated by a laser. These results demonstrate that the laser irradiation was able to increase the graphitization degree of the CFs, which showed some properties comparable to graphite fibers.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.375.2-375.2
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• 2016

그래핀(Graphene)은 원자 한 층 두께의 얇은 특성에 기인하여 우수한 투과도(~97.3%)를 나타내며, 높은 전자 이동도($200,000cm^2V^{-1}s^{-1}$)로 인하여 전기 전도도가 우수한 2차원 전자소재이다. 또한 유연하고 우수한 기계적 물성을 가지고 있어 실제로 다양한 소자에서 활용되고 있다. 그래핀을 이용하여 다양한 소자로 응용하기 위한 과정 중 하나인 포토리소그래피 공정(Photolithography process)은 원하는 패턴을 만들기 위해 제작하고자 하는 기판 위에 포토레지스트(Photoresist)를 코팅하는 과정을 거치게 된다. 하지만 이러한 과정은 소자 제작에 있어서 포토레지스트 잔여물을 남기게 된다. 그래핀 위에 남은 포토레지스트 잔여물은 그래핀의 우수한 전기적 특성을 저하시켜 소자특성에 불이익을 주게 된다. 본 연구에서는 수소 플라즈마를 이용하여 그래핀 위에 남은 중합체(Polymer) 잔여물을 제거한다. 사용한 그래핀은 화학 기상 증착법(Chemical vapor deposition)을 이용하여 성장시켰으며, PMMA(Poly(methyl methacrylate))를 이용하여 이산화규소(silicon dioxide) 기판에 전사하였다. 그래핀의 손상 없이 중합체 잔여물을 제거하기 위해 플라즈마 처리시간을 15초부터 1분까지 늘려가며 연구를 진행하였으며, 플라즈마 처리 시간에 따른 중합체 잔여물의 제거 정도와 그래핀의 보존 여부를 확인하기 위해 라만 분광법(Raman spectroscopy)과 원자간력현미경(Atomic force microscopy)을 사용하였다. 본 연구 결과를 통해 간단한 플라즈마 처리로 보다 나은 특성의 그래핀 소자를 얻게 됨으로써, 향상된 특성을 가진 그래핀 소자로 산업적 응용 가능성을 높일 수 있을 것이라 생각된다.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.281.1-281.1
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• 2016

Transition metal dichalcogenides (TMDCs) are promising layered structure materials for next-generation nano electronic devices. Many investigation on the FET device using TMDCs channel material have been performed with some integrated approach. To use TMDCs for channel material of top-gate thin film transistor(TFT), the study on high-k dielectrics on TMDCs is necessary. However, uniform growth of atomic-layer-deposited high-k dielectric film on TMDCs is difficult, owing to the lack of dangling bonds and functional groups on TMDC's basal plane. We demonstrate the effect of remote oxygen plasma pretreatment of large area synthesized few-layer MoSe2 on the growth behavior of Al2O3, which were formed by atomic layer deposition (ALD) using tri-methylaluminum (TMA) metal precursors with water oxidant. We investigated uniformity of Al2O3 by Atomic force microscopy (AFM) and Scanning electron microscopy (SEM). Raman features of MoSe2 with remote plasma pretreatment time were obtained to confirm physical plasma damage. In addition, X-ray photoelectron spectroscopy (XPS) was measured to investigate the reaction between MoSe2 and oxygen atom after the remote O2 plasma pretreatment. Finally, we have uniform Al2O3 thin film on the MoSe2 by remote O2 plasma pretreatment before ALD. This study can provide interfacial engineering process to decrease the leakage current and to improve mobility of top-gate TFT much higher.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.652-652
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• 2013

The conventional thermal chemical vapor deposition (CVD) setup for the graphene synthesis has mainly used convective heat transfer in order to heat a catalyst (e.g. Cu) up to $1,000^{\circ}C$. Although the conventional CVD has been so far widely accepted as the most appropriate candidate enabling mass-production of high-quality graphene, this method has stillremained under the standard for the commercialization largely due to the poor productivity arisen out of the required long processing time. Here, we introduced a fast and efficient synthetic route toward CVD-graphene. Unlike the conventional CVD using convection heat transfer, we adopted a CVD setup utilizing conduction heat transfer between Cu catalyst and rapid heating source. The high thermal conductive nature of Cu and the employed rapid heating source led to the remarkable reduction in processing timeas compared to the conventional convection based CVD (Fig. 1A), moreover, the synthesized graphene was turned out to have comparable quality to that synthesized by the conventional CVD (Fig. 1B). For the optimization of the conduction based CVD process, the parametric studies were thoroughly performed using through Raman spectroscopy and electrical sheet resistance measurement. Our approach is thought to be worth considerable in order to enhance productivity of the CVD graphene in the industry.