• The Journal of Information Technology
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• v.4 no.4
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• pp.51-63
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• 2001

Residue Number System has carry free operation and parallelism each modulus, So it is used for special purpose processor such as Digital Signal Processing and Neuron Processor. Magnitude comparison and sign detection are in need of Mixed Radix Conversion, and these operations are impediment to improve the operation speed. So in this Paper, MRC(Mixed Radix Converter) is designed using modified partitioned residue to speed up the operation of MRC, so it has progressed maximum twice operation time but increased the size of converter comparison to other converter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.3
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• pp.517-524
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• 2001

This paper describes a design of radix-2 SRT divider unit, which supports IEEE-754 floating-point standard, using redundant binary number system (RBNS). With the RBNS, the partial quotient decision logic can operate about 20-% faster, as well as can be implemented with a simple hardware when compared to the conventional methods based on two's complement arithmetic. By using a new redundant binary adder proposed in this paper, the mantissa divider is efficiently implemented, thus resulting in about 20% smaller area than other works. The divider unit supports double precision format, five exceptions and four rounding modes. It was verified with Verilog HDL and Verilog-XL.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.454-460
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• 2003

In this paper, we present a novel method of parallelization of the modular multiplication algorithm to improve time and space complexity on RNS (Residue Number System). The parallel algorithm executes modular reduction using new table lookup based reduction method. MRS (Mixed Radix number System) is used because algebraic comparison is difficult in RNS which has a non-weighted number representation. Conversion from residue number system to certain MRS is relatively fast in residue computer. Therefore magnitude comparison is easily Performed on MRS. By the analysis of the algorithm, it is known that it requires only 1/2 table size than previous approach. And it requires 0(ι) arithmetic operations using 2ㅣ processors.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1025-1031
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• 2007

This paper proposes an area-efficient pipeline FFT processor for MIMO-OFDM systems with four transmitting and four receiving antennas. Since the MIMO-OFDM system transmits multiple data streams, the complexity for the MIMO-OFDM system with a single-channel FFT processor increases linearly with the increase of the number of transmit channels. The proposed FFT processor is based on multi-channel structure, and therefore it can efficiently support multiple data streams. With the mixed radix algorithm, the number of non-trivial multiplications of the proposed FFT processor is decreased. The proposed FFT processor is synthesized with CMOS $0.18{\mu}m$ process and reduces the logic gates by 25% over a 4-channel Radix-4 multi-path delay commutator (R4MDC) FFT processor. Since the MIMO-OFDM FFT processor is one of the largest modules in the systems, the proposed FFT processor will be a vast contribution improvement to the low complexity design of MIMO-OFDM systems.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.279-284
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• 2003

In this paper, we propose an efficient architecture for radix-4 modular multiplication in systolic array structure based on the Montgomery's algorithm. We propose a radix-4 modular multiplication algorithm to reduce the number of iterations, so that it takes (3/2)n+2 clock cycles to complete an n-bit modular multiplication. Since we can interleave two consecutive modular multiplications for 100% hardware utilization and can start the next multiplication at the earliest possible moment, it takes about only n/2 clock cycles to complete one modular multiplication in the average. The proposed architecture is quite regular and scalable due to the systolic array structure so that it fits in a VLSI implementation. Compared to conventional approaches, the proposed architecture shows shorter period to complete a modular multiplication while requiring relatively less hardware resources.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1739-1747
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• 2004

In this paper, an efficient radix-4 systolic VLSI architecture for RSA public-key cryptosystem is proposed. Due to the simple operation of iterations and the efficient systolic mapping, the proposed architecture computes an n-bit modular exponentiation in n$^{2}$ clock cycles since two modular multiplications for M$_{i}$ and P$_{i}$ in each exponentiation process are interleaved, so that the hardware is fully utilized. We encode the exponent using Radix-4. SD (Signed Digit) number system to reduce the number of modular multiplications for RSA cryptography. Therefore about 20% of NZ (non-zero) digits in the exponent are reduced. Compared to conventional approaches, the proposed architecture shows shorter period to complete the RSA while requiring relatively less hardware resources. The proposed RSA architecture based on the modified Montgomery algorithm has locality, regularity, and scalability suitable for VLSI implementation.

• Journal of the Korean Mathematical Society
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• v.41 no.6
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• pp.945-955
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• 2004

In this paper, we establish a number system in $R^n$ which arises from a Haar wavelet basis in connection with decompositions of certain Cuntz algebra representations on $L^2$( $R^n$). Number systems in $R^n$ are also of independent interest [9]. We study radix-representations of $\chi$ $\in$ $R^n$: $\chi$:$\alpha$$_{ι}$ $\alpha$$_{ι-1}$…$\alpha$$_1$$\alpha$$_{0}$ ㆍ$\alpha$$_{-1}$ $\alpha$$_{-2}$ … as $\chi$= $M^{ι}$$\alpha$$_{ι}$ $\alpha$＋…M$\alpha$$_1$＋$\alpha$$_{0}$ ＋ $M^{-1}$ $\alpha$$_{-1}$ ＋ $M^{-2}$ $\alpha$$_{-2}$ ＋… where each $\alpha$$_{k}$ $\in$ D, and D is some specified digit set. Our analysis uses iteration techniques of a number-theoretic flavor. The view-point is a dual one which we term fractals in the large vs. fractals in the small,illustrating the number theory of integral lattice points vs. fractions.s vs. fractions.

• Journal of the Korea Society of Computer and Information
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• v.12 no.3
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• pp.37-50
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• 2007

In this paper, we designed and implementation of the high speed neuron processor for real time object recognition in the making automatic system. and we designed of the PE(Processing Element) used residue number system without carry propagation for the high speed operation. Consisting of MAC(Multiplication and Accumulation) operator using residue number system and sigmoid function operator unit using MAC(Mixed Radix conversion) is designed. The designed circuits are descript by C language and VHDL(Very High Speed Integrated Circuit Hardware Description Language) and synthesized by compass tools and finally, the designed processor is fabricated in $0.8{\mu}m$ CMOS process. we designed of MAC operation unit and sigmoid proceeding unit are proved that it could run time 0.6nsec on the simulation and improved to the speed of the three times and decreased to hardware size about 50%, each order. The designed neuron processor can be implemented of the object recognition in making automatic system with desired real time processing.

• The Journal of the Korea Contents Association
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• v.8 no.3
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• pp.41-46
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• 2008

Many methods have been developed to overcome the PAPR(peak-to-average power ratio) problem. Selective mapping(SLM), partial transmit sequence(PTS), subblock phase weighting(SPW) and gradient descent(GD) are used widely to reduce the PAPR. In this paper, we present an effective PAPR reduction method that decreases the number of calculations through Radix-2 DIF IFFT procedure and GD method that transmits selected data sequence. The data sequence is constructed by choosing elements that satisfy threshold value as one part of the sequence and the rest elements of each sequence are chosen to have the lower papr operating, which yields performance improvement.