• Proceedings of the Korea Information Processing Society Conference
• /
• 2011.11a
• /
• pp.56-58
• /
• 2011

원자력 발전소의 오작동이나 사고는 인명이나 재산상의 큰 피해를 초래하므로 엄격한 안전 기준을 적용하고 있다. 따라서 원자력 발전소의 안전성과 관련된 원전용 제어기는 높은 수준의 신뢰도와 안전도가 요구된다. 이를 위해 디지털 방식의 제어기에 PLC 방식의 제어기와 PLD 방식의 제어기를 사용하여 다양성을 얻고 있다. 본 논문에서는 PLD 방식의 원전용 트립제어기의 Functional Verification을 위하여 RTL 수준의 설계에 대한 Functional Coverage 분석을 사용하였다. 테스트벤치는 System Verilog에서 제공되는 클래스에 기반한 구조적 테스트벤치를 작성하여 사용하였다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2004.05a
• /
• pp.157-160
• /
• 2004

본 논문은 미국 차세대 디지털 케이블 방송 표준 규격인 오픈케이블($OpenCable^{TM}$)의 수신제한 모듈인 CableCard의 Physical Layer를 SystemC의 TLM(Transaction Level Modeling)과 RTL(Register-Transfer Level) 모델링 기법으로 설계하였다. 본 논문에서 설계한 CableCard의 Physical Layer는 PCMCIA Interface, Command Inteface 그리고 MPEG-2 TS Interface 로 구성된다. CableCard가 전원이 인가될 때, 카드 초기화를 위하여 동작하는 PCMCIA 인터페이스는 16 비트 PC 카드 SRAM 타입으로 2MByte Memory와 100ns access time으로 동작할 수 있게 설계하였다. PCMCIA 카드 초기화 동작이 완료된 후, CableCard의 기능을 수행하기 위하여 두 개의 논리적 인터페이스가 정의되는데 하나는 MPEG-2 TS 인터페이스이고, 다른 하나는 호스트(셋톱박스)와 모듈 사이의 명령어들을 전달하는 명령어 인터페이스(Command Interface)이다. 명령어 인터페이스(Command Interface)는 셋톱박스의 CPU와 통신하기 위한 1KByte의 Data Channel과 OOB(Out-Of-Band) 통신을 위한 4KByte의 Extended Channel 로 구성되고, 최대 20Mbits/s까지 동작한다. 그리고 MPEG-2 TS는 100Mbits/s까지 동작을 수행할 수 있게 설계하였다. 설계한 코드를 실행한 후, Cadence사의 SimVision을 통해서 타이밍 시뮬레이션을 검증하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2006.05a
• /
• pp.957-960
• /
• 2006

In this paper, we studied the location estimation algorithm of a spatial 3 dimension which extend the location estimation algorithm of a plane 2 dimension in 2.45GHz band RTLS(Real time location system). We used TDOA scheme which need not a time of transmission information of the tag and estimated 3 dimension coordinates. Also, estimated intersection of hyperbolic curve to X, Y coordinate of the tag at 2D coordinates searching area, $300m\times300m$ and LOS propagation environments. And, we estimated Z coordinate ultimately using X, Y coordinate. The location estimation algorithm of a spatial 3 dimension satisfies the RTLS specification requirement, 3m radius accuracy. From the result, we confirm that the location of tag which similar to actual coordinate in the case to an ideal received offset. However, we verified that the location of tag which escapes from a radius 3m within error range when received offset increased. Therefore, as the future work we are consider enhanced location accuracy of a spatial 3 dimension in RTLS system which using the decrease scheme of reader offset or the discriminate scheme of the estimation location.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.5 no.2
• /
• pp.89-101
• /
• 2005

Research on highly abstracted system modeling and simulation has received a great deal of attention as of the concept of platform based design is becoming ubiquitous. From a practical design point of view, such modeling and simulation must consider the following: (i) fast simulation speed and cycle accuracy, (ii) early availability for early stage software development, (iii) inter-operability with external tools for software development, and (iv) reusability of the models. Unfortunately, however, all of the previous works only partially addresses the requirements, due to the inherent conflicts among the requirements. The objective of this study is to develop a new system design methodology to effectively address the requirements mentioned above. We propose a new transaction-level system modeling methodology, called ViP (Virtual Platform). We propose a two-step approach in the ViP method. In phase 1, we create a ViP for early stage software development (before RTL freeze). The ViP created in this step provides high speed simulation, lower cycle accuracy with only minor modeling effort.(satisfying (ii)). In phase 2, we refine the ViP to increase the cycle accuracy for system performance analysis and software optimization (satisfying (i)). We also propose a systematic ViP modeling flow and unified interface scheme based on utilities developed for maximizing reusability and productivity (satisfying (ii) and (iv)) and finally, we demonstrate VChannel, a generic scheme to provide a connection between the ViP and the host-resident application software (satisfying (iii)). ViP had been applied to several System-on-a-chip (SoC) designs including mobile applications, enabling engineers to improve performance while reducing the software development time by 30% compared to traditional methods.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.153-156
• /
• 2000

This paper presents a SOC design methodology using the newly-emerging SystemC. The suggested methodology firstly uses SystemC to define blocks from the previously-developed system level algorithm with internal behavior and interface being separated and validate such a described blocks' functionality when integrated. Next, the partitioning between software and hardware is considered. With software, the interface to hardware is described cycle-accurate and the other internal behavior in conventional ways. With hardware, I/O transactions are refined gradually in several abstraction levels and internal behavior described on a function basis. Once hardware and software have been completed functionally, system performance analysis is performed on the built model with assumed performance factors and influences such decisions regressively as on optimum algorithm selection, partitioning and etc. The analysis then gives constraint information when hardware description undergoes scheduling and fixed-point trans- formation with the help of automatic translation tools or manually. The methodology enables C/C++ program developers and VHDL/Verilog users to migrate quickly to a co-design & co-verification environment and is suitable for SoC development at a low cost.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38C no.1
• /
• pp.97-108
• /
• 2013

Recently, mobile devices were increased and there was a sharp rise in demand. To exploit the location information of each device, many researcher was studying locating systems. The favorite locating or positioning systems were a GPS using satellites and a RTLS using wireless communication between devices. If some obstacle existed nearby the target device, The system have difference of performance. The obstacles near targets were caused signal disconnection and reflection because of NLOS condition. As the result, the NLOS condition degrade the locating performance. In this paper, we propose a locating system which is cooperated two systems using information reliability estimates from LOS/NLOS condition. We developed proposed system. In addition, we performed fields test and simulation tests at various environment for performance evaluation. As the result, the test showed 97% success rate to estimate NLOS condition. Furthermore, the simulation result of our locating system was increased to 89% compared with a single system.

• Journal of Korean Society for Geospatial Information Science
• /
• v.16 no.3
• /
• pp.43-49
• /
• 2008

The Real Time Location System (RTLS) is very important in the ubiquitous society for real time tracking of men, high price assets, and logistics products. In this work, we developed an active RF system for RTLS and tested its performance. The RTLS system developed in this work was constructed of three active readers and one active tag. The small size tag developed in this work operated with a coin type battery. To make the tag smaller, we used an internal PCB antenna and a chip antenna. We tested the performance of the tag. To reduce the manufacturing cost of our RF system, we used low price RF transceiver CC2510 chip-set. The CC2510 chip-set provided RSSI(Received Signal Strength Indicator) signal which could be used to determine the distances between an active tag and three active readers.

• Journal of Embryo Transfer
• /
• v.13 no.3
• /
• pp.301-312
• /
• 1998

To efficiently separate a protein stimulating sperm swim-up migration and movement from follicular proteins, the effect of paper chromatography and liquid chromatography with reverse phase column and superose column on protein separation was examined. And the results obtained were as follows; 1. The band component that was separated with paper chromatography stimulated sperm migration and movement depending on its additional levels. Especially, band I component significantly increased sperm migration. But, all components of bands 1, 2 and 3 showed lower sperm migration and movement, compared to follicular fluid at the same additional level. 2. Among the components separated from follicular protein of 2~5mm follicles with reverse phase column ($\mu$RPC), components at retention time (RT) of 3.33, 7.00, 13.87, and 16.6A minutes stimulated sperm migration within a limited range. 3. All components separated from follicular protein of 10mm follicles with $\mu$RPC column didn't stimulate sperm migration and movement. 4. Among the components separated from follicular protein of 2~5m follicles with superose column, components at retention volume (RV) of 1.35 and 0.82 ml significantly stimulated sperm migration and movement. In conclusion, protein components stimulating sperm migration and movement were efficiently separated with superose column in Smart system. Especially, components of RV 1.35 and RV0.82 stimulated sperm swim-up separation.

• Journal of Korean Society of Disaster and Security
• /
• v.9 no.1
• /
• pp.33-38
• /
• 2016

Real time location system was development for safety management at road and bridge maintenance field. The system can check the real-time location detection, movement history, behavior of a number of laborers. The system consisted of a Bluetooth and ZigBee that uses low-power. It had a very large error that the previous method for the position recognition by triangulation using the RSSI. Because This study proposed a new distance measurement and correction scheme using RSSI and accelerometer. It was evaluated in the maintenance field. A development system were evaluated in the field, the results are shown an error between 0.2 m and 0.4 m. And through the acceleration of history it was confirmed by determining possible to determine the safety situation of the laborers.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2002.11a
• /
• pp.63-68
• /
• 2002

JPEG2000은 기존의 정지영상압축부호화 방식에 비해 우수한 비트율-왜곡(Rate-Distortion)특성과 향상된 주관적 화질을 제공하며 인터넷, 디지털 영상카메라, 이동단말기, 의학영상 등 다양한 분야에서 적용될 수 있는 새로운 정지영상압축 표준이다. 본 논문에서는 SoC(System on a Chip)설계를 고려한 JPEG2000 인코더의 구조를 제안하고 IP(Intellectual Property)를 설계 및 검증하였다. 구현된 JPEG2000 IP는 DWT(Discrete Wavelet Transform)블록, 스칼라양자화블록, EBCOT(Embedded Block Coding with Optimized Truncation)블록으로 구성되어 있다. IP는 모의실험을 통해 구현 구조에 대한 타당성을 검증하였고, 반도체설계자산연구센터에서 제시한 'RTL Coding Guideline'에 따라 HDL을 설계하였다. 특히, DWT블록은 구현시 많은 연산과 메모리 용량이 필요하므로 영상을 저장할 외부 메모리를 사용하였고, 빠른 곱셈과 덧셈연산을 위한 3단 파이프라인 부스곱셈기(3-state pipeline booth multiplier)와 캐리예측 덧셈기(carry lookahead adder)를 사용하였다. 설계된 JPEG2000 IP들은 삼성 0.35$\mu\textrm{m}$ 라이브러리를 이용하여 Synopsys사 Design Analyzer 틀을 통해 논리 합성하였으며, Xillinx 100만 게이트 FPGA칩에 구현하여 그 동작을 검증하였다. 또한, Hard IP 설계를 위해 Avanti사의 Apollo툴을 이용하여 Layout을 수행하였다.