• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2181-2186
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• 2006

In this paper, a RTL binding technique for CPLD constraint is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in used CLB.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.799-802
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• 1998

본 논무은 HLS에서 CPLD 조건식을 고려한 RTL바인딩 기술로서 HDL로 기술된 회로의 스케쥴링을 한후 모듈 연산 간격을 고려하여 합당한 모듈을 선택하고 스케쥴링과 할당을 수행한 후 주어진 조건식에 맞도록 CPLD를 선정한다. 또한 할당된 결과의 모듈을 CPLD 내부의 CLB의 크기를 고려하여 부울식을 분할하고 최적의 CLB를 사용하여 회로를 구현할 수 있도록 binding 알고리즘을 제안하였다.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.1-6
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• 2006

In this paper, a RTL binding technique and low power technology mapping consider CPLD is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD consider low power. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in the power consumption by 43% comparing with that of non application algorithm.