• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.139-147
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• 2010

A novel turbo coded modulation scheme, called turbo-APPM, for deep space optical communications is constructed. The constructed turbo-APPM is a serial concatenations of turbo codes, an accumulator and a pulse position modulation (PPM), where turbo codes act as an outer code while the accumulator and the PPM act together as an inner code. The generator polynomial and the puncturing rule for generating turbo codes are chosen to show the low bit error rate. At the receiver, the joint decoding is performed by exchanging soft information iteratively between the inner decoder and the outer decoder. In the outer decoder, a local iterative decoding for turbo codes is conducted before transferring soft information to the inner decoder. Poisson distribution is used to model the deep space optical channel. It is shown by simulations that the constructed turbo-APPM provides coding gains over all previously proposed schemes such as LDPC-APPM, RS-PPM and SCPPM.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2983-2985
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• 2005

There are many factors to degrade the performance of power-line communication systems such as multi-path fading, attenuation, colored and impulsive noise, and interference. Most of all, impulsive noise is generated by switching operation of many power supply units and equipments, and it causes both burst error and random error as the pattern of generation. In this paper, the variations of performance for RS convolutional concatenated coded system are simulated and analysed with the several parameters over impulsive noise channel.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.34-43
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• 1994

The unequal symbol error probability of TCM(trellis coded modulation) is analyzed and applied to the derivation of bit error probability of /RS/Trellis concatenated coded-modulation system. An upper bound of the symbol error probability of TCM concatenated with RS code is obtained by exploiting the unequal symbol error probability of TCM, and it is applied to the derivation of the upper bound of the bit error probability of the RS/Trellis concatenated coded-modulation system. Our upper bounds of the concatenated codes are tighter than the earlier established other upper bounds.

• Journal of the Korea Concrete Institute
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• v.28 no.5
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• pp.571-579
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• 2016

RS-LMC (Rapid Setting Latex Modified Concrete) has been widely used as repair material for bridge deck overlay or rehabilitation, because the overlaid pavement could be opened to the traffic after 3 hours of curing. Although the field performance of RS-LMC generally indicates that it has an excellent bonding to the substrate and shows a long term performance, the crack by vibration of vehicles have been happened on the overlay of bridges in technical reports. In this study, experimental research was carried out to evaluate the vibration properties of RS-LMC overlays by using P.S.T (Pavement Shaking Table). Total 12 specimens were tested and the variables are Latex-cement ratio (L/C) and amplitude of vibration. The result shows that the number of cracks and the total length of cracks are reduced as the increase of Latex-cement ratio (L/C) until 15%. And the crack occurs at a very small strain than the proposed values by Walter, D, G and design codes.

• Journal of Korea Multimedia Society
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• v.13 no.8
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• pp.1163-1170
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• 2010

In this paper, in order to develop a remote progress management system through the Internet, we show a design method to make easy maintenance by developing the system with both the JAVA language and GoF Design Patterns. For the system implementation, we added the RS232C and RS422/RS485 communication modules to PLC(Programmable Logic Controller) in the control box which provide the real time status data of machines. Also we set up the RS232C to Ethernet converter based on wireless environment to communicate the PLC control data. We use JAVA Swing components to implement the multi-tier architecture system supported the GUI of the Applet and Frame at the same time so that the manager grasps the progress of work easily at the remote machines through the Internet. The key objective of the multi-tier architecture is to share resources among clients, this proposed system can help to develop the software to control the remote machine, and also it has the advantage that developer who wants to make a similar software can make easy to add new function reusing the existing codes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10A
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• pp.809-815
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• 2011

In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability t of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as t increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the proposed architecture can be used for a high-speed RS decoder with less gate count.

• Journal of Broadcast Engineering
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• v.8 no.4
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• pp.437-451
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• 2003

With the rapid growth of internet technologies and wide availability of multimedia computing facilities, the enforcement of multimedia copyright protection becomes an important issue. Digital watermarking is viewed as an effective way to deter content users from illegal distributions. In recent years, digital watermarking has been intensively studied to achieve this goal. However, when the watermarked media is transmitted over the channels modeled as the additive white Gaussian noise (AWGN) channel, the watermark information is often interfered by the channel noise and produces a large number of errors. So many error-correcting codes have been applied in the digital watermarking system to protect the embedded message from the disturbance of the noise, such as BCH codes, Reef-Solomon (RS) codes and Turbo codes. Recently, low-density parity-check (LDPC) codes were demonstrated as good error correcting codes achieving near Shannon limit performance and outperforming turbo codes nth low decoding complexity. In this paper, in order to mitigate the channel conditions and improve the quality of watermark, we proposed the application of LDPC codes on implementing a fairly robust digital image watermarking system. The implemented watermarking system operates in the spectrum domain where a subset of the discrete wavelet transform (DWT) coefficients is modified by the watermark without using original image during watermark extraction. The quality of watermark is evaluated by taking Into account the trade-off between the chip-rate and the rate of LDPC codes. Many simulation results are presented in this paper, these results indicate that the quality of the watermark is improved greatly and the proposed system based on LDPC codes is very robust to attacks.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.21-28
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• 1993

Decoding algorithm of noncyclic Reed-Solomon codes consists of four steps which are to compute syndromes, to find error-location polynomial, to decide error-location, and to solve error-values. There is a decoding method by which the computation of both error-location polynomial and error-evaluator polynimial can be avoided in conventional decoding methods using Euclid algorithm. The disadvantage of this method is that the same amount of computation is needed that is equivalent to solve the avoided polynomial. This paper considers the division method on polynomial on GF(2$^{m}$) systematically. And proposes a novel method to find error correcting polynomial by simple mathematical expression without the same amount of computation to find the two avoided polynomial. Especially. proposes the method which the amount of computation to find F (x) from the division M(x) by x, (x-1),....(x--${\alpha}^{n-2}$) respectively can be avoided. By applying the simple expression to decoding procedure on RS codes, propses a new decoding algorithm, and to show the validity of presented method, computer simulation is performed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.193-202
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• 2010

This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4C
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• pp.365-373
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• 2003

In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.