• The KIPS Transactions:PartA
• /
• v.11A no.1
• /
• pp.81-88
• /
• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.6
• /
• pp.1575-1582
• /
• 1998

Reed-Solomon(RS) code which is especially effective against burst error is studied as a forward error correction technique in this ppaer. The circuits of RS encoder and decoder for ASIC implementation are designed and presented employing modified Euclid's algorithm. The functionalities of the designed circuits are verified though C programs which simulates the circuits over the various errors and erasures. The pipelined circuits using systolic arrays are designed for ASIC realization in VHDL, and verified through the logic simulations. Finally the circuit synthesis of RS encoder and decoder can be achieved.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.11
• /
• pp.13-20
• /
• 2005

For Modern Consumer and Communication Elecronic Devices, Always Error Protecting HW and SW is used. The Core is RS(Reed Solomon) Codec in Galois Field GF($2^8$). Here New 2 to 3 Symbol RS Decoder Design and Encoder design Method using Normalized error position Value is described. Examples are given to show the methods are working well.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.1C
• /
• pp.8-13
• /
• 2006

A new RS(Reed Solomon) Decoder design method, using Galois Subfield GF($2^4$) Multiplier, is described. The Decoder is designed using Normalized error position stored ROM. Here New Inverse Calculator in GF($2^8$) is designed, which is simpler and faster than the classical GF($2^8$) direct inverse calculator, using the Galois Subfield GF($2^4$) Arithmatic operator.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.11
• /
• pp.39-46
• /
• 1997

In this paper, we propose an area-efficient architecture of a reed-solomon (RS) decoder/encoder for digital VCRs. The new architecture of the decoder/encoder targeted to reduce the circit size and decoding latency has the following two features. First, area-efficeincy has been significantly improved by sharing a functional block for encoding, modified syndrome computation, and erasure locator polynomial evaluation. Second, modified euclid's algorithms has been implemented by using a new architecture. Experimental results have showed that the decoder/encoder designed by using the proposed method has been implemented with 25% smaller sie over straight forware implementation based on the conventional method [1] and the decoding latency has been reduced.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.7
• /
• pp.1506-1511
• /
• 2004

The error control of digital transmission system is a very important subject because of the noise effects, which is very sensitive to transmission performance of the digital communication system It employs a modified Euclid's algorithm to compute the error-location polynomial and error-magnitude polynomial of input data. The circuit size is reduced by selecting the Modified Euclid's Algorithm with one Euclid Cell of mutual operation. And the operation speed of Decoder is improved by using ROM and parallel structure. The proposed Encoder and Decoder are simulated with ModelSim and Active-HDL and synthesized with Synopsys. We can see that this chip is implemented on Xilinx Virtex2 XC2V3000. A share of slice is 28%. nut speed of this paper is 45Mhz.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.38 no.2
• /
• pp.195-199
• /
• 2010

(255,223) RS(Reed-Solomon) code which is the CCSDS(Consultative Committee for Space Data Systems) standard was used in the STSAT-3 to correct errors during the downlink of payload data. The RS encoder developed by VHDL was implemented in MMU(Mass Memory Unit). Moreover, the RS decoder developed by C-language was implemented in the DRS(Data Receiving System) of ground station. In this paper, we reported the design and analysis results of RS(255,223) for STSAT-3. The BER(Bit Error Rate) performance from MMU to DRS was confirmed through the downlink test at 16 Mbps. Also, the error correction performance and capability of RS(255,223) was tested by the manual attenuation of the RF(Radio Frequency) signal in the X-band transmitter resulting in putting some errors in the communication line.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.281-284
• /
• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk with double error detecting and correcting capability. A variety of error correction codes(ECCs) have been used in magnetic recordings, and optical recordings. Among the various types of ECCs, Reed Solomon(RS) codes has emerged as one the most important ones. The most complex circuit in the RS decoder is the part for finding the error location numbers by solving error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid's algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and peformed logic synthesis using the SYNOPSYS CAD tool. The total umber of gate is about 11,000 gates.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.2
• /
• pp.10-17
• /
• 1989

The Berlekamp-Massey algorithm, the method of using the Euclid algorithm, and Fourier transforms over a finite field can be used for the decoding of Reed-Solomon codes (called RS codes). RS codes can also be decoded by the algorithm that was developed by Peterson and refined by the Gorenstein and Zierler. However, the decoding of RS codes using the Peterson-Gorenstein-Zieler algorithm offers sometimes computational or implementation advantages. The decoding procedure of the double-error correcting (31,27) Rs code over the symbol field GF ($2^5$) will be analyized in this paper. The complete analysis, gate array design, and implementation for encoder/decoder pair of (31.27)RS code are performed with a strong theoretical justification.

• Journal of Digital Convergence
• /
• v.12 no.3
• /
• pp.269-275
• /
• 2014

The DAB system was designed to provide CD quality audio and data services for fixed, portable and mobile applications with the required BER below $10^{-4}$. However for the T-DMB system with the video service of MPEG-4 stream, BER should go down $10^{-8}$ by adding FEC blocks which consist of the Reed-Solomon (RS) encoder/decoder and convolutional interleaver/deinterleaver. In this paper we propose two types of turbo coded T-DMB system without altering the puncturing procedure and puncturing vectors defined in the standard T-DMB system for compatibility. One(Type 1) can replace the existing RS code, convolutional interleaver and RCPC code by a turbo code and the other one (Type 2) can substitute the existing RCPC code by a turbo code. Simulation results show that two new turbo coded systems are able to yield considerable performance gain after just 2 iterations. Type 2 system is better than type 1 but the amount of performance improvement is small.