• Archives of Plastic Surgery
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• v.51 no.1
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• pp.52-61
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• 2024

Background Although prepectoral implant-based breast reconstruction has recently gained popularity, dual-plane reconstruction is still a better option for patients with poor-quality mastectomy skin flaps. However, shoulder morbidity is aggravated by subpectoral reconstruction, especially in irradiated patients. This study aimed to demonstrate shoulder exercise improvement in subpectoral reconstruction by delayed prepectoral conversion with an acellular dermal matrix (ADM) inlay graft technique at the time of expander-to-implant exchange after irradiation. Methods Patients with breast cancer treated for expander-to-implant exchange after subpectoral expander insertion and subsequent radiotherapy between January 2021 and June 2022 were enrolled. An ADM inlay graft was inserted between the pectoralis major muscle and the previously inserted ADM. The ADM was sutured partially overlapping the pectoralis muscle from the medial side with the transition part, to the muscle border at the lateral side. Perioperative shoulder joint active range-of-motion (ROM) for forward flexion, abduction, and external rotation was also evaluated. Results A total of 35 patients were enrolled in the study. Active shoulder ROM significantly improved from 163 degrees preoperatively to 176 degrees postoperatively in forward flexion, 153 to 175 degrees in abduction, and 69 to 84 degrees in external rotation. There was no difference in patient satisfaction regarding the final outcome between the conventional prepectoral reconstruction group and the study group. Conclusion Shoulder exercises in irradiated patients who underwent subpectoral reconstruction were improved by delayed prepectoral conversion using an ADM inlay graft. It is recommended that subpectoral reconstruction not be ruled out due to concerns regarding muscle contracture and shoulder morbidity in radiation-planned patients with poor mastectomy skin flaps.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1880-1885
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• 1989

In this paper, a new approach for systolic array realizing the discrete cosine transform (DCT) based on discrete Fourier transform (DFT) of an input sequence is presented. The proposed array is based on a simple modified DFT(MDFT) version of the Goertzel algorithm combined with Kung's approach and is proved perfectly. This array requires N cells, one multiplier and takes N clock cycles to produce a complete N-point DCT and also is able to process a continuous stream of data sequences. We have analyzed the output signal-to-noise ratio(SNR) and designed the circuit level layout of one-PE chip. The array coefficients are static adn thus stored-product ROM's can be used in place of multipliers to limit cost as eliminate errors due to coefficients quantization.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.116-119
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• 2000

The Process of Inner Product has been widely used in a DSP. But it is difficult to implement by a dedicated hardware because it needs many computation steps for multiplication and addition. To reduce these steps, it is essential to design efficient hardware architecture. This paper proposes the design method of adder-based distributed arithmetic for implementation of DCT module and the automatic design of summation-network which is a core block in the proposed design method. Finally, it shows that the proposed design method is more efficient than a ROM-based distributed arithmetic which is the typical design method.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.327-330
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• 2008

This paper shows an implementation of WLAN-based Audio/Video(A/V) system for multimedia home networks. Proposed WLAN-based A/V system can transmit multimedia data of high quality. The entire system consists of a 16-bit RISC controller, a program ROM, a SRAM, timers, an interrupt controller, a DART, GPIOs, an I2C and the OFDM modem supporting for the IEEE 802.11g standard. The simple MAC functions are implemented by firmware on an embedded 16-bit RISC controller. The OFDM modem supports a complete set of data rates up to 54Mbps. Proposed the system is implemented by an Altera FPGA EP1S60F1020C6 device, a 10-bit 2-ch DAC, a 10-bit 2-ch ADC and RF/IF chips.

• Korean Journal of Applied Biomechanics
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• v.34 no.1
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• pp.18-24
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• 2024

Objective: The purpose of this study was to evaluate the effects of an 8-week velocity-based training on the maximum vertical jump in elite sprinters. Method: Ten elite sprinters were participated in this study (age: 21 ± 0.97 yrs., height: 179 ± 3.54 cm, body mass: 72 ± 2.98 kg). An 8-week velocity-based power training was provided to all subjects for twice per week. Their maximum vertical jumps were measured before and after velocity-based training. A 3-dimensional motion analysis with 8 infrared cameras and 4 channels of EMG was performed in this study. A paired t-test was used for statistical verification. The significant level was set at α=.05. Results: There were no statistically significant differences were found between pre and post the training (p>.05). However, most variables included jump record, knee joint ROM, and muscle activation of rectus femoris showed increased pattern after the training. Conclusion: In this study, an 8-week velocity-based training did not showed the significant training effects. However, knee joint movement which is the key role of the vertical jump revealed positive kinematic and kinetic pattern after the training. From this founding, it is believed that velocity-based training seems positively affect the vertical jump which is the clear measurement of mechanical power of sprinter. In addition, to get more clear evidence of the training more training period would be needed.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2002.11a
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• pp.360.1-360
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• 2002

Current information storage devices, such as HDD, CD/DVD-ROM/RW, probe-based memory and cabon nano tubes, are compared with biological information storage mechanisms in DNA and brain memory. Various biological components in living cells are analyzed based on "irreducible complexity" of intelligent design concept. Linear and arel density of information stored in the biological and mechanical storages are compared for the applications and developments of new storage devices.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.30-39
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• 1994

A 1-chip high quality binarizing VLSI image processor (which has 8 bit ADC. 6 bit flash ADC, 15K standard cell, and 1K word ROM) based on 10 MIPS 16 bit DSP is implemented for FAX. This image processor(IP) performs image pre-processing. image quality improvement in copying and sending mode, and mixed image processing based on the fuzzy theory. And smoothing in sub-scan direction is applied for normal receiving mode data so the received data is enhanced like fine mode data. Each algorithm is processed with the same type of image processing window and 2-D image processing is implemented with a 1-D line buffer. The fabricated chip is applied to a FAX machine and image quality improvement is verified.

• Journal of information and communication convergence engineering
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• v.11 no.3
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• pp.199-206
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• 2013

An emergency monitoring system for the elderly, which uses acceleration data measured with an accelerometer, angular velocity data measured with a gyroscope, and heart rate measured with an electrocardiogram, is proposed. The proposed fall detection algorithm uses multiple parameter combinations in which all parameters, calculated using tri-axial accelerations and bi-axial angular velocities, are above a certain threshold within a time period. Further, we propose an emergency detection algorithm that monitors the movements of the fallen elderly person, after a fall is detected. The results show that the proposed algorithms can distinguish various types of falls from activities of daily living with 100% sensitivity and 98.75% specificity. In addition, when falls are detected, the emergency detection rate is 100%. This suggests that the presented fall and emergency detection method provides an effective automatic fall detection and emergency alarm system. The proposed algorithms are simple enough to be implemented into an embedded system such as 8051-based microcontroller with 128 kbyte ROM.

• Proceedings of the KIEE Conference
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• 1985.07a
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• pp.257-261
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• 1985

This paper deals with the personal computer based design for the sequential machines. Most part of sequential machine design have been implemented by using general purpose microprocessors in order to obtain the specific unctions required for their system. But, they have some difficulties in design stages. Knowledge of systems design method and high technology are basically applied to all the design stages.. Therefore ready made microcomputer system for personal use, personal computer, can be transformed to sequential machines by using the corresponding softwares and built-in personal computer input/output ports. Following the state transition diagram or table, we can obtain the ROM type of sequential machines directly and need not to design input/output interface except actuators and samplers because of capability of personal computer. Our main purpose of this design method are quick, flexible, reliable, modifiable circuit design of the sequential machines. In this paper, we use APPLE-II plus personal computer as target machine.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.61-69
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• 2010

In this paper, an 1.2V 8b 800MSPS A/D Converter(ADC) with an odd number of folding block to overcome the asymmetrical boundary-condition error is described. The architecture of the proposed ADC is based on a cascaded folding architecture using resistive interpolation technique for low power consumption and high input frequency. The ADC employs a novel odd folding block to improve the distortion of signal linearity and to reduce the offset errors. In the digital block, furthermore, we use a ROM encoder to convert a none-$2^n$-period code into the binary code. The chip has been fabricated with an $0.13{\mu}m$ 1P6M CMOS technology. The effective chip area is $870{\mu}m\times980{\mu}m$. SNDR is 44.84dB (ENOB 7.15bit) and SFDR is 52.17dBc, when the input frequency is 10MHz at sampling frequency of 800MHz.