• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.186-193
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• 2019

This paper presents and implements a simple programmable PCM encoder structure uisng the commutation method. In the telemetry system, information is required to assign each data to the channel in order to generate a frame format the data acpuired from the sensor. In this case, when the number of state information is large or the data type is various, there is a necessity to input a large amount of information to each channel. However, the more the number of channels and data, the more probability the error will occur. Therefore, in this paper, the channel information is created using the program. And PCM encoder was implemented to store channel information in ROM. The proposed PCM encoder architecture reduces the likelihood of errors. And it can improve the development speed. The validity of proposed structure is proved by simulation.

• Journal of the Korea Computer Industry Society
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• v.2 no.9
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• pp.1183-1190
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.289-293
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• 2009

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.

• Journal of Advanced Navigation Technology
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• v.24 no.4
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• pp.305-313
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• 2020

Telemetry system is a system that transmits status information data acquired from the aircraft to the ground station. PCM encoder needs memory to store channel information in order to generate a frame format using the acquired data. Generally, telemetry systems in large aircraft require much larger memory for the increased acquisition channel information due to the increased sensors and subsystems. However, they have difficulty to store all channel information in limited memory. In this paper, we suggests and implements an advanced PCM encoder that can efficiently manage memory by minimizing duplicated channel information. This novel PCM encoder allocates duplicated channel information to memory only once. And, sub commutation channels having different information for each minor frame are allocated to the memory by multiples of sub commutation channels. Finally, the suggested PCM encoder was proved by simulation that composed channels of various measurement cycles.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.8-13
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• 2006

A new RS(Reed Solomon) Decoder design method, using Galois Subfield GF($2^4$) Multiplier, is described. The Decoder is designed using Normalized error position stored ROM. Here New Inverse Calculator in GF($2^8$) is designed, which is simpler and faster than the classical GF($2^8$) direct inverse calculator, using the Galois Subfield GF($2^4$) Arithmatic operator.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.5
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• pp.485-490
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• 2004

This paper presents a new interpolation algorithm for measuring high resolution position information which is prepared to a nino servo control motor using analog quadrature encoder. In the past, there are large capacity of memory(ROM or RAM) and two high price and resolution A/D(Analog-to-Digital Converter) for sensing two quadrature signals from a analog sinusoidal encoder interpolation. But high resolution of position from sinusoidal encoder can be obtained by using only small capacity of memory, one A/D converter and comparator. Experimental results show that the proposed algorithm is useful for measuring high resolution position.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.169-172
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1506-1511
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• 2004

The error control of digital transmission system is a very important subject because of the noise effects, which is very sensitive to transmission performance of the digital communication system It employs a modified Euclid's algorithm to compute the error-location polynomial and error-magnitude polynomial of input data. The circuit size is reduced by selecting the Modified Euclid's Algorithm with one Euclid Cell of mutual operation. And the operation speed of Decoder is improved by using ROM and parallel structure. The proposed Encoder and Decoder are simulated with ModelSim and Active-HDL and synthesized with Synopsys. We can see that this chip is implemented on Xilinx Virtex2 XC2V3000. A share of slice is 28%. nut speed of this paper is 45Mhz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.6
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• pp.84-89
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• 2003

In this paper, we real-time implemented to the TMS320C5416 the vocoder of variable bit rate applied the SOLA-B algorithm by Henja to the ITU-T G.729A vocoder of 8kbps transmission rate. This proposed method using the SOLA-B algorithm is that it is reduced the duration of the speech in encoding and is played at the speed of normal by extending the duration of the speech in decoding. At this time, we bandied that the interval of cross correlation function if skipped every 3 sample for decreasing the computational amount of SOLA-B algorithm. The real-time implemented vocoder of C.729A and SOLA-B algorithm is represented the complexity of maximum that is 10.2MIPS in encoder and 2.8MIPS in decoder of 8kbps transmission rate. Also, it is represented the complexity of maximum that is 18.5MIPS in encoder and 13.1MIPS in decoder of 6kbps, it is 18.5MIPS in encoder and 13.1MIPS in decoder of 4kbps. The used memory is about program ROM 9.7kwords, table ROM 4.5kwords, RAM 5.1 kwords. The waveform of output is showed by the result of C simulator and Bit Exact. Also, for evaluation of speech quality of the vocoder of real-time implemented variable bit rate, it is estimated the MOS score of 3.69 in 4kbps.

• Journal of Korea Multimedia Society
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• v.8 no.7
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• pp.882-888
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• 2005

MPEG-2 Advanced Audio Coding (AAC) has already been standardized as a sophisticated next generation technology AAC provides an audio signal that has CD quality at 96-128kbps/stereo. This paper describes a high-quality and efficient software implementation of an MPEG-2 AAC LC Profile encoder. Common scalefactor and noisless coding are accelerated by $45\%$ and $27\%$, respectively, through the use of TMS320C30 instructions. The implemented encoder uses 7.5kWords of program memory, 18kWords of data ROM and 92kBytes of data RAM, respectively. The results of subjective Qualify test showed that the sound quality achieved at 96kbps/stereo was equivalent to that of MP3 at 128kbps/stereo.