• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.27-32
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• 2022

RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.81-86
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• 2023

Recently, demand for embedded systems requiring low power and high specifications has been increasing, and RISC-V processors are being widely applied. RISC-V, a RISC-based open instruction set architecture (ISA), has been developed and researched by UC Berkeley and other researchers since 2010. RV32I ISA is sufficient to support integer operations such as addition and subtraction instructions, but M-extension should be defined for multiplication and division instructions. This paper proposes an RV32I, RV32IM processor, and indicates benchmark performance scores compared to an existing processor. Additionally, A non-stalling method was proposed to support a 2-stage pipelined DSP multiplier to the 5-stage pipelined RV32IM processor. Proposed RV32I and RV32IM processors satisfied a maximum operating frequency of 50 MHz on Artix-7 FPGA. The performance of the proposed processors was verified using benchmark programs from Dhrystone and Coremark. As a result, the Coremark benchmark results of the proposed processor showed that it outperformed the existing RV32IM processor by 23.91%.

• Journal of the Semiconductor & Display Technology
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• v.23 no.3
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• pp.1-6
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• 2024

Recent research on embedded systems has become increasingly important due to their central role in high-performance embedded devices, including artificial intelligence, autonomous driving, and energy management technologies. Embedded systems are specialized computer systems designed to perform specific tasks while optimizing performance and minimizing memory usage. RISC-V, an open RISC-based instruction set architecture developed by the University of Berkeley in 2010, is well-suited for these systems. In addition to the base 32-bit integer instruction set, RISC-V supports extensions such as the M-extension for multiplication and division and the C-extension for instruction compression. In this paper, we propose the design of a 32-bit 5-stage pipeline RV32IMC processor aimed at high-performance embedded devices. By incorporating the RV32IMC instruction set, the proposed processor achieves enhanced computational efficiency and reduced code size, making it a strong candidate for energy-efficient, high-performance embedded applications. Furthermore, the design was validated on an Artix-7 field-programmable gate array, demonstrating the processor's feasibility and potential benefits for embedded systems.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.341-344
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• 1999

본 논문에서는 DSP 기능을 내장한 32비트 RISC 마이크로프로세서를 위한 버스 제어기를 설계하였다. 연구의 초점은 버스 타이밍, 주소 멀티플렉싱, 리프레쉬, 버스 중재 등을 제어하는 버스제어기를 온칩화 하여 CPU로 하여금 외부 램과 추가적인 장치없이 직접 연결될 수 있도록 한 것이다. 버스 제어기가 관리하는 메모리의 종류는 SRAM, ROM, DRAM, EDO DRAM이며 고속 모드(Fast page mode, EDO page mode 및 RAS-down mode)기능을 지원하며 다양한 Wait를 넣을 수 있다. 주소 영역은 4가지(EMAO-EMA3)이며 내부적으로 7개 의 레지스터가 있고 이들을 이용하여 서로 연결된 세 개의 상태 머신으로 모든 램과의 타이밍을 제어함으로써 공유블록을 활용할 수 있었다. Verilog HDL의 기술하고 Synopsys로 합성한 후 타이밍 검증을 수행한 결과 최악조건에서 53.1㎒로 동작할 수 있었다. 그 후 0.6㎛ single poly triple metal process 공정으로 레이아웃 되었고 면적은 44㎜ × 1.21㎜ 이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.83-90
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• 2004

In this paper, we proposed a new instruction set(X32Y ISA) with 3 different types of instruction mode. The proposed instruction set organizes 32-bit, 24-bit, 16-bit instruction in order to solves a problem of memory size limitation in an embedded microprocessor. We designed a 32-bit 5 stage pipeline RISC microprocessor based on the X32V ISA. To verify the proposed the X32V ISA and a microprocessor, we estimated a program code size of multimedia application programs using a X32V simulator. In result, we verified that the Light mode and the Ultra Light mode obtains 8%, 27% reduction of a program code size through comparison with the Default mode. The proposed microprocessor was verified all X32V instructions execution at Xilinx FPGA with 33MHz operating frequency,

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.68-75
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• 2009

As the recent performance of microprocessor is improving quickly, the necessity of cache is growing because of the increase of the access time of main memory. Every block of direct-mapped cache maps to one cache line. Although the mapping rule is simple, if different blocks map to one cache line, the miss ratio will be higher than the set-associative cache due to conflicts. In this paper, for the improvement of the direct-mapped cache of OpenRISC, 4-way set-associative cache is proposed. Four blocks of the main memory of the proposed cache map to one cache line so that the miss ratio is less than the direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The OpenRISC core including the 4-way set-associative cache was verified with FPGA emulation. As the result of performance measurement using test program, the performance of the OpenRISC core including the 4-way set-associative cache is higher than the previous one by 50% and the decrease of miss ratio is more than 15%.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.466-468
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• 2000

ARM 프로세서는 CISC 보다는 간단하게 디자인된 RISC로서 내장 응용프로그램에 적합하기 때문에 앞으로 모든 디지털 기기에 ARM 코어를 기반으로 한 핵심 칩들이 생산된다. 그러나 명령어가 CISC보다는 적기 때문에 주어진 작업에 대해 완전한 처리를 위해서는 보다 많은 명령어들을 필요로 한다. 이러한 ARM 프로세서에서 데이터를 전송할 때 사용하는 메모리 영역과 레지스터들을 프로그램과 함께 분석하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.814-821
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• 2012

We propose a network processor called an OmniFlow processor capable of wire-speed flow management by a hardware-based flow admission control(FAC) in this paper. Because the OmniFlow processor can set up and release a wire-speed connection for flows, the update period of flows can be set to a short time, and only active flows can be effectively managed by terminating a flow that does not have a packet transmitted within this period. Therefore, the FAC can be used to provide a reliable transmission of UDP as well as TCP applications. This processor is fabricated in 65nm CMOS technology, and total gate count is 25 million. It has 40 Gb/s throughput performance in using the 32 RISC cores when maximum operating frequency is 555MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2569-2578
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• 2009

Core-A microprocessor is the all-Korean product designed as 32-bit embedded RISC microprocessor developed by KAIST and supported by the Industrial Property Office. This paper analyze Core-A microprocessor architecture and proposes efficient method to interface Core-A microprocessor with coprocessor. To verify proposed interfacing method, the AES cryptography processor that has 128-bit key and block size is used as a coprocessor. Coprocessor and AES are written in Verilog-HDL and verified using Modelsim simulator. It except AES module consists of about 3,743 gates and its maximum operating frequency is about 90Mhz under 0.35um CMOS technology. The proposed coprocessor interface architecture is efficiency to send data or to receive data from Core-A to coprocessor.

• ETRI Journal
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• v.10 no.3
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• pp.24-35
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• 1988

본 논문은 한국전자통신연구소에서 개발하고 있는 RISC 형태의 32비트 프로세서인 HARP(High-performance Architecture for Risc-type Processor)의 파이프라인 설계와 익셉션 처리 방법에 관한 것이다. HARP의 파이프라인은 명렁어 페치의 병목현상을 해결하기 위하여 중첩된 메모리 액세스 방법을 사용하며 이는 5단계로 구성된다. 그리고 명령어 동시 수행으로 인해 발생하는 자원 충돌을 해결하기 위하여 bypassing logic, instruction fetch unit 및 code-reorganizer를 사용한다. 명령어 수행시 파이프라인 상에서 발생하는 익셉션에 대해서는 익셉션 처리의 복잡성을 피하기 위하여 instruction restart 방법을 사용한다.