• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.288-292
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• 2002

We propose the new type of on-chip ESD protection method for RF applications. By using the properties of RF circuits, we can use the short-circuited stub as ESD protection device in front of the DC blocking capacitor Specially, we can use short-circuited stub as the portion of the matching circuit so to reduce the and various parameters of the transmission line. This new type ESD protection method is very different from the conventional ESD protection method. With the new type ESD protection method, we remove the parasitic capacitance of ESD protection device which degrade the performance of core circuit.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.24-25
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• 2008

An Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics, especially for RF (Radio Frequency) integrated circuits (ICs). This paper reviews design and analysis of on-chip ESD (electrostatic discharge) protection circuits for RF applications. Key issues in RF ESD protection, design methods, and RF ESD protection solutions are discussed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.36-46
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• 2010

In multi-GHz RF ICs and high-speed digital interfaces, ESD protection devices introduce considerable parasitic capacitance and resistance to inputs and outputs, thereby degrading the RF performance, such as input/output matching, gain, and noise figure. In this paper, the impact of ESD protection devices on the performance of RF ICs is investigated and design methodologies to minimize this impact are discussed. With RF and ESD test results, the 'RF/ESD co-design' method is discussed and compared to the conventional RF ESD protection method which focuses on minimizing the device size.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.401-410
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• 2017

In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the $V_{DD}$ and $V_{SS}$ buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.172-180
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• 2003

Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF ICs. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/40 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1567-1570
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• 2022

This paper, we presents a RF protection technique of antenna switch by improving the power handling capability in worst case environment mode for mobile phone applications without critical payment of circuit performances such as insertion loss, isolation and ACBV (AC breakdown voltage). By applying a additional capacitive path located in front of the antenna in cell-phone, it performs the effective reduction of input power in high voltage standing wave ratio (VSWR) condition. Under the all-path off condition which causes a high VSWR, it achieved 37.7dBm power handling level as high as 5.7dB compared to that of conventional one at 2GHz. In addition, insertion loss and isolation performances were 0.31dB and 42.72dB at 2 GHz, respectively which were almost similar to that of the conventional circuit. The proposed antenna switch was fabricated in 130nm CMOS SOI technology.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.2
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• pp.287-293
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• 2009

This paper would suggest about data communicate using RF Transmitter-Receiver and about PC protection method authenticate using software of PC which Receiver is connected. Older PC protection system is demanded manual operation of the user but the suggesting method protect PC automatically with judge existing of the user who has Tag approaches the distance which gets near. And it is impossible about the forgery and it is safe about sniffing attack and spoofing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.75-87
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• 2010

For two input-protection schemes suitable for RF ICs utilizing the thyristor and diode protection devices, which can be fabricated in standard CMOS processes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit for an input HBM test environment of a CMOS chip equipped with the input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain the characteristic differences of two protection schemes as an input ESD protection circuit for RF ICs, and suggest valuable guidelines relating design of the protection devices and circuits.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.136-144
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• 2004

From the AC analysis results utilizing a two dimensional device simulator, the ac equivalent-circuit modeling of the ESD protection devices is executed. It is explained that the ac equivalent circuit of the NMOS protection transistor is modeled by a rather complicated form and that, depending on the frequency range, the error can be large if it is modeled by a simple RC serial circuit. It is also shown that the ac equivalent circuit of the thyristor-type pnpn protection device can be modeled by a simple RC serial circuit. Based on the circuit simulations utilizing the extracted equivalent circuits, the effects of the parasitics in the protection device on the characteristics of LNA are examined when the LNA, which is one of the important RF circuits, is equipped with the protection device. It is explained that a large error can result in estimating the circuit characteristics if the NMOS protection transistor is modeled by a simple capacitor. It is also confirmed that the degradation of the LNA characteristics by incorporating the ESD protection device can be reduced a lot by adopting the suggested pnpn device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.3
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• pp.422-429
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• 2022

In this paper, the intermediate frequency transmission signal level between the network system-based baseband and RF unit consisting of multi-channel airborne relay devices and a lot of mission devices, which are currently undergoing technology development tasks, is kept constant at the reference signal level. Considering the other party's receiving input range, despite changes in the short-range long-range wireless communication environment, it presents a multi-link protection and MLP-A algorithm that allows signals to be transmitted stably and reliably through signal detection automatic gain control, and experiments and analysis considering short-distance and long-distance wireless environments were performed by designing, manufacturing, and implementing RF units to which MLP-A algorithms were applied, and applying distance calculation equations to the configuration of multiple air movements and verification networks. Through this, it was confirmed that a stable and reliable RF communication system can be operated.