• 제목/요약/키워드: RF circuit

검색결과 682건 처리시간 0.03초

Design of RE-DC conversion circuit for the batteryless Transponder

  • Jin, In-su;Yang, Kyeong-rok;Ryu, Hyoung-sun;Kim, Yang-mo
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 ITC-CSCC -2
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    • pp.1001-1004
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    • 2000
  • RFID system is applied to identify, locate and track people, cars, animals. In RFID system, the passive transponder without battery has some benefits than active transponder, such as no restriction in battery exchange and in battery’s life. But it needs auxiliary RF-DC conversion circuit. RF-DC conversion circuit originated from Wireless Power Transmission (WPT). In this paper, RF-DC conversion circuit consists of a microstrip patch antenna and impedance matching circuit, Cock-croft Walton circuit. And RF-DC conversion circuits have two kinds of T-type and Cross-type impedance matching circuits.

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Equivalent Circuit Parameters of S-band 1.5 Cell RF Gun Cavity

  • Kim, Ki-Young;Kang, Heung-Sik;Tae, Heung-Sik
    • Journal of electromagnetic engineering and science
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    • 제4권1호
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    • pp.30-36
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    • 2004
  • We determined equivalent circuit parameters of a 1.5 cell S-band RF gun cavity from the resonant characteristics of its decoupled cavities(half cell and full cell) using the code SUPERFISH. Equivalent circuit parameters of the 1.5 cell RF gun cavity resonated in the 0-mode were obtained easily from the circuit parameters of each decoupled cavities. In order to obtain equivalent circuit parameters for the $\pi$ -mode cavity, we calculated the differences of the resonant frequencies and the equivalent resistances between the 0- and $\pi$ -modes with slight variations of the radius and thickness of the coupling iris. From those differences, we obtained R/Q value and equivalent resistance of the $\pi$ -mode, which are directly related to the equivalent circuit parameters of the coupled cavity. Using calculated R/Q value, we can express equivalent inductance, capacitance and resistances of the RF gun cavity resonated in the $\pi$ -mode, which can be useful for analyzing coupled cavities in a steady state.

대칭적인 스위치 구조 기반 RF 플라즈마 시스템 적용 전기적 가변 커패시터 (Electrical Variable Capacitor based on Symmetrical Switch Structure for RF Plasma System)

  • 민주화;채범석;김현배;서용석
    • 전력전자학회논문지
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    • 제24권3호
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    • pp.161-168
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    • 2019
  • This study introduces a new topology to decrease the voltage stress experienced by a 13.56 MHz electrical variable capacitor (EVC) circuit with an asymmetrical switch structure applied to the impedance matching circuit of a radio frequency (RF) plasma system. The method adopts a symmetrical switch structure instead of an asymmetrical one in each of the capacitor's leg in the EVC circuit. The proposed topology successfully reduces voltage stress in the EVC circuit due to the symmetrical charging and discharging mode. This topology can also be applied to the impedance matching circuit of a high-power and high-frequency RF etching system. The target features of the proposed circuit topology are investigated via simulation and experiment. Voltage stress on the switch of the EVC circuit is successfully reduced by more than 40%.

Passive 트랜스폰더의 RF-DC 변환회로에 대한 설계 및 분석 (The Design and Analysis of RF-DC conversion circuit in the Passive Tranponder)

  • 진인수;김종범;양경록;김양모
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 하계종합학술대회 논문집
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    • pp.757-760
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    • 1999
  • Depending upon the existence of the battery, transponder is divided into active and passive transponder. The passive transponder operates without battery and so has no limitation in its operating range and life time. But it needs the RF-DC conversion circuit. In this paper, the analysis and design of the RF-DC conversion circuit in passive transponder operated in high frequency is presented and is confirmed by simulation and experiment.

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RF IC 설계를 위한 새로운 CMOS RF 모델 (A New CMOS RF Model for RF IC Design)

  • 박광민
    • 대한전자공학회논문지SD
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    • 제40권8호
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    • pp.555-559
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    • 2003
  • 본 논문에서는 CMOS 소자의 RF 동작을 정확히 예측하기 위해 Si 표면에서의 메탈 라인 사이의 커패시턴스 효과와 표피효과 및 근접효과를 포함한 RF IC 설계를 위한 새로운 CMOS RF 모델을 처음으로 제시하였다. Si 표면에서의 메탈 라인 사이의 커패시턴스는 레이아웃에 기초하여 모델링하였으며, 표피효과는 메탈 라인의 등가회로에 병렬회로를 부가하여 사다리꼴 등가회로로 구현하였다. 근접효과는 사다리꼴 등가회로에서 교차 결합된 인덕턴스 사이의 상호 인덕턴스를 부가함으로써 모델링하였다. 제안된 RF 모델은 BSIM 3v3에 비해 측정 데이터와 잘 일치하였으며, GHz 영역에서 소자 동작의 주파수 종속성을 잘 보여주었다.

DC voltage control by drive signal pulse-width control of full-bridged inverter

  • Ishikawa, Junichi;Suzuki, Taiju;Ikeda, Hiroaki;Mizutani, Yoko;Yoshida, Hirofumi
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1996년도 Proceedings of the Korea Automatic Control Conference, 11th (KACC); Pohang, Korea; 24-26 Oct. 1996
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    • pp.255-258
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    • 1996
  • This paper describes a DC voltage controller for the DC power supply which is constructed using the full-bridged MOS-FET DC-to-RF power inverter and rectifier. The full-bridged MOS-FET DC-to-RF inverter consisting of four MOSFET arrays and an output power transformer has a control function which is able to control the RF output power when the widths of the pulse voltages which are fed to four MOS-FET arrays of the fall-bridged inverter are changed using the pulse width control circuit. The power conversion efficiency of the full-bridged MOS-FET DC-to-RF power inverter was approximately 85 % when the duty cycles of the pulse voltages were changed from 30 % to 50 %. The RF output voltage from the full-bridged MOS-FET DC-to-RF inverter is fed to the rectifier circuit through the output transformer. The rectifier circuit consists of GaAs schottky diodes and filters, each of which is made of a coil and capacitors. The power conversion efficiency of the rectifier circuit was over 80 % when the duty cycles of the pulse voltages were changed from 30 % to 50 %. The output voltage of the rectifier circuit was changed from 34.7V to 37.6 V when the duty cycles of the pulse voltages were changed from 30 % to 50 %.

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고주파통신회로 설계를 위한 CMOS RF 모델 파라미터 (The CMOS RF model parameter for high frequency communication circuit design)

  • 여지환
    • 한국산업정보학회논문지
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    • 제6권3호
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    • pp.123-127
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    • 2001
  • CMOS 트랜지스터의 등가회로모델 파라미터 $C_{gs}$ 의 예측방법이 CMOS 트랜지스의 반전층내의 유동전하량 계산과 전하유도 특성에 의해 제안되었다. 이 $C_{gs}$ 파라미터는 MOS 트랜지스터의 RF대역의 차단주파수를 결정하고 또한 입력과 출력을 커플링 시키는 중요한 파라미터이다. 이 제안된 방법은 등가회로 모델에서 파라미터 값을 예측하고 파라미터 값을 추출하는 소프트웨어 개발에 기여할 것이다.

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A Layout-Based CMOS RF Model for RFIC's

  • Park Kwang Min
    • Transactions on Electrical and Electronic Materials
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    • 제4권3호
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    • pp.5-9
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    • 2003
  • In this paper, a layout-based CMOS RF model for RFIC's including the capacitance effect, the skin effect, and the proximity effect between metal lines on the Si surface is proposed for the first time for accurately predicting the RF behavior of CMOS devices. With these RF effects, the RF equivalent circuit model based on the layout of the multi-finger gate transistor is presented. The capacitances between metal lines on the Si surface are modeled with the layout. And the skin effect is modeled to the equivalent ladder circuit of metal line. The proximity effect is modeled by adding the mutual inductance between cross-coupled inductances in the ladder circuit representation. Compared to the BSIM 3v3 and other models, the proposed RF model shows better agreements with the measured data and shows well the frequency dependent behavior of devices in GHz ranges.

Testing and Self Calibration of RF Circuit using MEMS Switches

  • Kannan, Sukeshwar;Kim, Bruce;Noh, Seok-Ho;Park, Se-Hyun
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2011년도 추계학술대회
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    • pp.882-885
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    • 2011
  • This paper presents testing and self-calibration of RF circuits using MEMS switches to identify process-related defects and out of specification circuits. We have developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated using an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. This test stimulus is provided as input to the RF circuit and peak-to-average ratio (PAR) is measured at the output. For a faulty circuit, a significant difference is observed in the value of PAR as compared to a fault-free circuit. Simulation is performed for various circuit conditions such as fault-free as well as fault-induced and their corresponding PARs are stored in the look-up table. This testing and self-calibration technique is exhaustive and efficient for present-day communication systems.

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A New Automatic Compensation Network for System-on-Chip Transceivers

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • ETRI Journal
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    • 제29권3호
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    • pp.371-380
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    • 2007
  • This paper proposes a new automatic compensation network (ACN) for a system-on-chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on-chip ACN using 0.18 ${\mu}m$ SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design-for-testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.

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