• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.632-638
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• 2011

This paper presents on-chip Design-for-Testability (DFT) circuit for radio frequency System-on-Chip (SoC) applications. The proposed circuit measures functional specifications of RF integrated circuits such as input impedance, gain, noise figure, input voltage standing wave ratio (VSWRin) and output signal-to-noise ratio (SNRout) without any expensive external equipment. The RF DFT scheme is based on developed theoretical expressions that produce the actual RF device specifications by output DC voltages from the DFT chip. The proposed DFT showed deviation of less than 2% as compared to expensive external equipment measurement. It is expected that this circuit can save marginally failing chips in the production testing as well as in the RF system; hence, saving tremendous amount of revenue for unnecessary device replacements.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.3
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• pp.1-7
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• 1999

A single RF transceiver evaluation board have been developed for the purpose of application to the 900MHz band transceiver contained RF-IC chip And environment test was evaluated. The RF-IC chipset includes LNA(Low Noise Amplifier), down-conversion mixer, AGC(Automatic Gain Controller), switched capacitor filter and down sampling mixer. The RF evaluation board for the testing of chipset contained various external matching circuits, filters such as RF/IF SAW(Surface Acoustic Wave) filter and duplexer and power supply circuits. With the range of 2.7~3.3V the operated chip revealed moderate power consumption of 42mA. The chip was well operated at the receiving frequency of 925~960MHz. Measurement result is similar to general RF receiving specification of the 900MHz digital mobile phone.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1925-1926
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• 2008

본 논문에서는 UHF TV방송 전 대역 Ch.14(473MHz)$\sim$Ch.69(803MHz)까지의 모든 채널에서 동작하는 유도결합구조의 RF동조회로를 설계하였다. 기존 자기결합구조의 RF동조회로는 PCB 양면을 사용하여야 하고 수작업으로 Air Coil 간격을 조절해야만 한다. 부품의 집적화와 양산 효율성 측면에서 자기결합구조의 단점을 해결할 수 있도록 하기 위해 본 논문에서 제안한 유도결합구조는 수동부품인 칩인덕터와 칩커패시터 및 가변용량 다이오드만을 사용하여 RF동조회로를 설계하였다. 칩인덕터는 Air Coil에 비해 낮은 소자 Q값을 가진다. 상대적으로 낮은 Q값을 갖는 칩인덕터를 사용하기 때문에 이를 보완하기 위해 Peaking용 칩인덕터를 설계 디자인에 적용하였다. 가변형 대역통과필터로 동작하기 위해 자기결합구조와 동일하게 가변용량 다이오드를 이용하였다. UHF TV방송 전 대역(470$\sim$806MHz)에서 -2.88 $\sim$ -3.97dB의 삽입손실 특성 및 -8dB 이상의 반사손실 특성과 330MHz의 중심주파수 변화 범위를 갖는다. 현재 상용중인 지상파 튜너에 적용되고 있는 자기결합구조의 RF동조회로를 대치하여 적용될 수 있을 것이다.

• Proceedings of the KAIS Fall Conference
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• 2010.05a
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• pp.124-127
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• 2010

본 논문에서는 소형 SMD 솔레노이드 형태의 RF 칩 인덕터의 최적 구조를 도출하였다. $1.0\times0.5\times0.5mm^3$ 크기의 96% $Al_2O_3$ 코아는 $40{\mu}m$ 직경의 구리 코일을 4회 권선하여 8.57nH의 인덕턴스, 37.6의 품질계수와 6.05GHz의 SRF를 가진다. $40{\mu}m$ 직경의 구리 코일을 0.35mm 솔레노이드 길이로 중앙에 6회 권선하였을 경우가 250MHz11.2nH의 인덕턴스, 29.8의 품질계수와 5.6GHz의 SRF로 가장 우수하였다.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1345-1346
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• 2006

본 논문에서는 솔레노이드 형태의 칩 인덕터와 나선형태의 박막 인덕터에 대하여 주파수 특성을 비교 분석하여 장 단점을 정의하고자 한다. 솔레노이드형 RF 칩 인덕터는 $1.0mm{\times}0.5mm{\times}0.5mm$의 크기에 11nH의 인덕턴스를 가질 수 있도록 6회 권선하였다. 나선형 박막 인덕터는 $213{\mu}m{\times}250{\mu}m{\times}304{\mu}m$의 크기에 11nH의 인덕턴스를 가질 수 있도록 7회 권선하였다. 시뮬레이션을 위하여 AnSoft사의 HFSS를 이용하였으며, 이 결과 솔레노이드형 RF 칩 인덕터는 2GHz에서 77 정도의 품질계수와 5.6GHz의 SRF를 가진다. 반면 나선형 박막 인덕터는 2GHz에서 14 정도의 품질계수와 4.5GHz의 SRF를 가진다. 성능면에서는 솔레노이드형 RF 칩 인덕터가 우수한 특성을 나타내었으나 크기를 감소시키는데 제한을 받으므로, 향후 소형 경량화를 위하여 박막 인덕터의 개발은 필수적이며, 성능을 더욱 향상시키기 위하여 나선형태와 재료의 개발이 필수적이라 하겠다.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.2
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• pp.27-31
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• 2003

RF characteristics of CPW(coplanar waveguide) pattern with bonding pads used in flip-chip packaging of GaAs is studied in the frequency range of 1 GHz to 35 GHz. Simulation, fabrication and evaluation are performed for the proposed patterns. Measurement results show proposed patterns have similar properties of $S_{11}$below -31 dB and $S_{21}$ above -0.19 dB with typical CPW In addition RF properties are improved with the increase of width of ground line. This indicates CPW structure with bonding pads keeps RF characteristics of typical CPW.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.964-970
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• 2013

This paper presents a bandpass wireless 3-D chip to chip interface technique. The proposed technique uses direct amplitude modulation of the free running oscillator which especially utilizes the coupling capacitance between two stacked chips as a part of the resonator. Therefore, the oscillator is three dimensionally configured and a simple envelope detector can be used as a receiver without any additional matching circuitry. The proposed link was designed and fabricated using 110 nm CMOS technology and experimental results successfully showed the data transmission at a data rate of 2 Gb/s for the stacked chips with a thickness of 50 ${\mu}m$ consuming 4.32 mW. The sizes of the Tx and Rx chips are 0.045 $mm^2$ and 0.029 $mm^2$, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1004-1007
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• 2005

This paper presents a programmable RF BIST (Built-in Self-Test) circuit for low noise amplifiers. We have developed a new on-chip RF BIST circuit that measures RF parameters of low noise amplifier (LNA) using only DC measurements. The BIST circuit contains test amplifier with programmable capacitor banks and RF peak detectors. The test circuit utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the mathematical equations. Our on-chip BIST can be self programmed for 1.8GHz, 2.4GHz and 5.25GHz LNA for GSM, Bluetooth and IEEE802.11g standards.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.202-211
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• 2000

Utilizing the circuit simulator SPICE, we designed a 1.9GHz CMOS up-conversion mixer and explained in detail the simulation procedures including device modeling for the circuit design. Since the measured characteristics of the chip fabricated using the $0.5{\mu}m$ standard CMOS process had shown a big deviation from the characteristics expected by the original simulations, we tried to figure out the proper reasons for the discrepancies. Simulations considering the discovered problems in the original simulations have shown the validity of the simulation method tried for the design. We have shown that the utilized standard CMOS process can be used for the implementation of the chip characteristics similar to those of the equivalent chip fabricated using the GaAs MESFET process.