• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.262-265
• /
• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

• Journal of applied mathematics & informatics
• /
• v.31 no.5_6
• /
• pp.785-794
• /
• 2013

Soon after Lee and O'Sullivan proposed a new interpolation algorithm for algebraic soft-decision decoding of Reed-Solomon codes, there have been some attempts to apply a coordinate transformation technique to the new algorithm, with a remarkable complexity reducing effect. In this paper, a conceptually simple way of applying the transformation technique to the interpolation algorithm is proposed.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.1C
• /
• pp.8-13
• /
• 2006

A new RS(Reed Solomon) Decoder design method, using Galois Subfield GF($2^4$) Multiplier, is described. The Decoder is designed using Normalized error position stored ROM. Here New Inverse Calculator in GF($2^8$) is designed, which is simpler and faster than the classical GF($2^8$) direct inverse calculator, using the Galois Subfield GF($2^4$) Arithmatic operator.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.8
• /
• pp.19-26
• /
• 1993

The bit error probability of Reed-Solomon/convolutional concatenated codes can be more exactly calculated by using a more approximate bound of the symbol error probability of the convolutional codes. This paper obtains the unequal symbol error bound of the convolutional codes, and applies to the calculation of the bit error probability of the concatenated codes. Our results are tighter than the earlier studied other bounds.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2009.06a
• /
• pp.31-32
• /
• 2009

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.938-941
• /
• 1999

In this paper, we designed a pipeline (15,9) Reed-solomon decoder. To compute the error locator polynomials, we used the Euclidean algorithm. This algorithm includes computation of inverse element. We avoided the inverse element calculation in this RS decoder by using ROMs. We designed this decoder using VHDL. Simulation results show that the designed decoder corrects three error symbols. We implemented this design through an Altera FPGA chip.

• Proceedings of the IEEK Conference
• /
• 2000.11c
• /
• pp.47-50
• /
• 2000

Recently many efforts on the development of automatic processing system for delivery sequence sorting have been performed in ETRI , which requires the use of postal 4-state bar code system to encode delivery points. The 4-state bar code called postal 4-state bar code for high speed processing that has been specifically designed for information processing of logistics and automatic processing of the mail items. This paper describes a method of Reed-Solomon encoding for creating error correction codeword of 4-state bar code.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.6B
• /
• pp.984-990
• /
• 2010

In Current Digital $C^3$ Devices(Communication, Computer, Consumer electronic devices), Reed-Solomon encoder is essentially used. For example we should use RS encoder in DSP LSI of CDMA Mobile and Base station modem, in controller LSI of DVD Recorder and that of computer memory(HDD or SSD memory). In this paper, we propose new economical multiplierless (also without divider) RS encoder design method. The encoder has Arbitrary parity positions.

• Journal of KSNVE
• /
• v.4 no.4
• /
• pp.425-433
• /
• 1994

A detailed investigation of a reed resonance for a vertical pump design has been conducted. The structural features of this class of pump lead to typical dynamic characteristics. Of particular importance is the fact that the pump assembly is suspended on a high column above the floor with a heavy motor on the top. Considerable amount of mass forces is involved and the vibration can cause damage to the pumps or to the foundation. It is shown that the reed resonance of the pump-motor system plays important role for design and troubleshooting purposes.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.11C
• /
• pp.649-654
• /
• 2011

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.