• Title/Summary/Keyword: RC parallel circuit

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Development of a High Voltage Semiconductor Switch for the Command Charging o (모듈레이터의 지령충전을 위한 고전압 반도체 스위치 개발)

  • Park, S.S.;Lee, K.T.;Kim, S.H.;Cho, M.H.
    • Proceedings of the KIEE Conference
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    • 1998.07f
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    • pp.2067-2069
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    • 1998
  • A prototype semiconductor switch for the command resonant charging system has been developed for a line type modulator, which charges parallel pulse forming network(PFN) up to voltage of 5 kV at repetition rates of 60 Hz. A phase controlled power supply provides charging of the 4.7 ${\mu}s$ filter capacitor bank to voltage up to 5 kV. A solid state module of series stack array of sixe matched SCRs(1.6 kV, 50 A) is used as a command charging switch to initiate the resonant charging cycle. Both resistive and RC snubber network are used across each stage of the switch assembly in order to ensure proper voltage division during both steady state and transient condition. A master trigger signal is generated to trigger circuits which are transmitted through pulse transformer to each of the 6 series switch stages. A pulse transformer is required for high voltage trigger or power isolation. This paper will discuss trigger method, protection scheme, circuit simulation, and test result.

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On a High-Speed Implementation of LILI-128 Stream Cipher Using FPGA/VHDL (FPGA/VHDL을 이용한 LILI-128 암호의 고속화 구현에 관한 연구)

  • 이훈재;문상재
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.11 no.3
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    • pp.23-32
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    • 2001
  • Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.