• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.1
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• pp.21-26
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• 2012

This paper presents a real-time image transferring and localization system utilizing HSDPA, a commercial wireless network system. A novel image compression algorithm is developed based on MPEG4 to comply with uploading bandwidth of 130 kbps and QVGA image transmission of 30 fps. Aiming at being embedded in moving vehicles, the proposed system has a small size, low power consumption, and robustness to disturbances. We validate the performance of the system by presenting captured images of transferring video and localization data. Our system can be applied to real-time surround monitoring in moving vehicles or real-time ecology observation in remote places.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.141-144
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• 2004

A QVGA active-matrix backplane is produced on a 25${\mu}m$ thin plastic substrate. A 4-mask photolithographic process is used. The insulator layer and the semiconductor layer are organic material processed from solution. This backplane is combined with the electrophoretic display effect supplied by SiPix and E ink, resulting in an electronic paper display with a thickness of only 100${\mu}m$. This is world's thinnest active-matrix display ever made.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1319-1322
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• 2007

Planar PIN photodiode is compatible with LTPS process, and its fabrication requires no additional manufacturing process. In this study we design the optimum dimension of PIN diodes with two nitride layers to improve the efficiency of PIN diodes. The PIN photo sensor shows very good sensitivity to ambient light illuminance.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1001-1004
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• 2008

An advanced backplane circuit technology for AMOLED using amorphous silicon TFTs with commercial level reliability, uniformity and lifetime was recently integrated into a prototype device. Differential aging of T98>100 hrs at 200 cd/m2 brightness and >10,000hrs lifetime is demonstrated. A 2.2" QVGA ($240{\times}320$) prototype has been developed and shown having the above-mentioned high performance.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.215-218
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• 2003

We have developed a reflective 3.5" QVGA color TFT-LCD with high reflection within viewing angle. For this, We have introduced new pixel design and asymmetric reflector. Based on these technical concepts, we get a high aperture ratio of 93.5% and much higher reflection up to 64% with a 3.5" prototype panel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2365-2373
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• 2011

This paper propose the hardware IP of real-time face detection system for mobile devices and digital cameras required for high speed, smaller size and lower power. The proposed face detection system is robust against illumination changes, face size, and various face angles as the main cause of the face detection performance. Input image is transformed to LBP(Local Binary Pattern) image to obtain face characteristics robust against illumination changes, and detected the face using face feature data that was adopted to learn and generate in the various face angles using the Adaboost algorithm. The proposed face detection system can be detected maximum 36 faces at the input image size of QVGA($320{\times}240$), and designed by Verilog-HDL. Also, it was verified hardware implementation by using Virtex5 XC5VLX330 FPGA board and HD CMOS image sensor(CIS) for FPGA verification.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.102-107
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• 2007

This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.77-82
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• 2008

H.264 is a video coding standard of ITU-T and ISO/IEC, and widely spreads its application due to its high compression ratio more than twice that of MPEG-2 and high image quality. It has different architecture depending on demands since it is a lied from small image of QVGA to large size of HD. In this paper, We propose a scalable architecture for intra-prediction of H.264 decoders. The proposed scheme has a scalable architecture that can accommodate up to 4 processing elements depending on performance demands and can reduce the number of access to memory using efficient memory management so as to be energy-efficient. We design the intra-prediction unit using Verilog-HDL and verily it by prototyping using an FPGA. The performance is analyzed using the results of design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.40-47
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• 2009

In this paper, we present the design of a source driver of QVGA scale TFT-LCD driver IC which uses a mixed driving method and performs $\gamma$-correction to improve image. The source driver with 240 RGB ${\times}$ 320 dots resolution drives a TFT-LCD panel through 720 channels and implements 262k colors using 18-bit RGB data format. The mixed driving method is a mixture the channel amp. driving method with high drivability and the gray amp. driving method with small area, which remarkably reduces channel driver areas. The driver has been designed using the $0.35{\mu}m$ Magnachip embedded DRAM technology and simulated using the HSPICE simulator. The results show that our source driver operates well with y-correction and the channel driver has $17{\mu}s$ channel driving time with only 78 driving amplifiers and control logic.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.64-69
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• 2013

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.