• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.1
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• pp.119-123
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• 2011

We have investigated the luminous efficiency of various cell resolution and structure from 50" FHD to 50" QFHD Plasma Display. The suggested test panels have two different cell array types which are the delta and matrix cell array type. The results showed that, in the case of the suggested QFHDs, the firing and sustain voltage were increased and voltage margin was decreased. These results are caused by the reduced wall voltage and increased charged particle loss, at the side wall. The luminance of the suggested QFHDs was lower from 20% to 40% than that of the suggested FHDs and the power consumption was higher from 42% to 83% than that of the suggested FHDs. In conclusion, the maximum luminous efficiency of the suggested QFHD(D110) has reached about 38%, compared with suggested FHDs($\fallingdotseq$ 2.7 lm/W).

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.155-164
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• 2015

This paper describes a design and implementation of CABAC decoder, which would handle HEVC syntax elements in adaptively pipelined-parallel computation manner. Even though CABAC offers the high compression rate, it is limited in decoding performance due to context-based sequential computation, and strong data dependency between context models, as well as decoding procedure bin by bin. In order to enhance the decoding computation of HEVC CABAC, the flag-type syntax elements are adaptively pipelined by precomputing consecutive flag-type ones; and multi-bin syntax elements are decoded by processing bins in parallel up to three. Further, in order to accelerate Binary Arithmetic Decoder by reducing the critical path delay, the update and renormalization of context modeling are precomputed parallel for the cases of LPS as well as MPS, and then the context modeling renewal is selected by the precedent decoding result. It is simulated that the new HEVC CABAC architecture could achieve the max. performance of 1.01 bins/cycle, which is two times faster with respect to the conventional approach. In ASIC design with 65nm library, the CABAC architecture would handle 224 Mbins/sec, which could decode QFHD HEVC video data in real time.