• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.145-148
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• 2007

The authors report on the fabrication of thin film transistors (TFTs) that use amorphous indium-gallium-zinc oxide (a-IGZO) channel and have the channel length (L) and width (W) patterned by dry etching. To prevent the plasma damage of active channel, a 100-nm-thckness $SiO_{x}$ by PECVD was adopted as an etch-stopper structure. IGZO TFT (W/L=10/50${\mu}m$) fabricated on glass exhibited the high performance mobility of $35.8\;cm^2/Vs$, a subthreshold gate voltage swing of $0.59V/dec$, and $I_{on/off}$ of $4.9{\times}10^6$. In addition, 4.1” transparent QCIF active-matrix organic light-emitting diode display were successfully fabricated, which was driven by a-IGZO TFTs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.5
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• pp.907-914
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• 1997

The conventional decoding procedure for the images encoded using fractal contractive transformation algorithms is performed by applying the transformations iteratively for an arbirary initial image. In this paper, we showed that the atractor image can be obtained analytically when the image is encoded using the fractal algorithm proposed by Monro and Dudbridge, in which the corresponding domain block for a range block is fixed. Using the analytical formula, we can obtain the attractor image without iteration procedure. Computer simulation results for various test images show that we can increase the image decoding speed by more than five times when we use the analytical formula compared to the previous iteration methods. Also we confirmed that the real time decoding by software on PD is possible for the moving picture with QCIF formats.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1C
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• pp.56-62
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• 2009

In H.264/AVC, rate distortion optimization algorithm is used to decide the best block mode from various block modes. It improves a bit rate but greatly increases an amount of computation. This paper proposes a fast rate distortion optimization algorithm that omits a rate distortion optimization adaptively by predicting its cost from the cost calculated for motion estimation. The simulation results show that the proposed algorithm, on average, keeps nearly the image quality and the bit rate made by the rate distortion optimization while reduces 69.86% and 69.63% of computation added by it in CIF and QCIF respectively.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.63-66
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• 2001

본 논문에서는 TI사의 TMS320C6201 DSP를 이용하여 H.263 동영상 부호화기를 실시간 구현하고자 한다. 구현한 부호화기는 QCIF 형식의 영상을 사용하여 ITU-T H.263 권고안의 기본 모드를 따라 주로 C 언어와 intrinsics를 사용하여 구현하였다. 특히, 속도 향상을 위해서 고속 메모리의 사용을 극대화하는데 중점을 두었고, 연산량이 많은 모듈에 대한 최적화와 데이터의 병렬 처리 및 DMA (Direct Memory Access) 전송 등을 고려하여 구현하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.5
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• pp.25-32
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• 1998

In this paper, SA (shape adaptive)-DCT is implemented using a datapath with 4 MACs (multiplication & accumulator). DCT is a well-known bottleneck of real-time video compression using MPEG-like schemes. High-speed pipelined MACs presented here implement real-time DCT. A datapath in this paper executes DCT/IDCT algorithms for QCIF 15fps(frame per second), maximum rate of VLBV(very low bitrte video) in MPEG-4. A 32bit accumulator in a MAC prevents distortion caused by fixed-point process. It can be applied to various operations such as ME (motion estimation) and MC(motion compensation) with a absolutor and a halfer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.102-107
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• 2007

This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.44-52
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• 2006

Recently developed MPEG-4 Part 2 compression standard provides a novel capability to handle arbitrary video objects. To support this capability, an efficient object segmentation technique is required. This paper proposes a real-time algorithm for foreground object segmentation in video sequences. The proposed algorithm consists of two steps: the first step that segments a video frame into multiple sub-regions using Spatio-Temporal Watershed Transform and the second step in which a foreground object segment is extracted from the sub-regions generated in the first step. For real-time processing, the algorithm is partitioned into hardware and software parts so that computationally expensive parts are off-loaded from a processor and executed by hardware accelerators. Simulation results show that the proposed implementation can handle QCIF-size video at 15 fps and extracts an accurate foreground object.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.4
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• pp.245-252
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• 2008

In this paper, we propose a new method for improving the H 264 encoding process and motion estimation part. Our approach is a method to reduce the encoding running time through the omission of reference frame in the mode selection process of H 264 and an improvement of SAD computing process. To evaluate the proposed method, we used the H 264 standard image of QCIF size and TIN 4:2:0 format. Experimental results show that proposed SAD algorithm 1 can improve the speed of encoding runnung time by an average of 4.7% with a negligible degradation of PSNR. However, SAD algorithm 2 can improve the speed of encoding runnung time by an average of 9.6% with 0.98dB degradation of PSNR.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.1018-1025
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• 2011

Scalable Video Coding (SVC) extension of H.264/AVC is a new video coding standard for media convergence by providing diverse videos of different spatial-temporal-quality layers with a single bitstream. Recently, real-time SVC codecs are being developed for the application areas of surveillance video and mobile video, etc. This paper presents the design and implementation of a H.264/SVC decoder based on an embedded DSP using Open SVC Decoder (OSD) which is a real-time software decoder designed for the PC environment. The implementation consists of porting C code of the OSD software from PC to DSP environment, profiling the complexity performance of OSD with further optimization, and integrating the optimized decoder into the TI Davinci EVM (Evaluation Module). 50 QCIF/CIF frames or 15 SD frames per second can be decoded with the implemented DSP-based SVC decoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.102-111
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• 2005

In this paper, we propose an advanced hardware architecture for the fast inter prediction engine of the video coding standard MPEG-4 AVC. We describe the algorithm and derive the hardware architecture emphasizing and real time operation of the quarter_pel based motion estimation. The fast inter prediction engine is composed of block segmentation, motion estimation, motion compensation, and the fast quarter_pel calculator. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur & Virtex2 FPGA, and also by synthesis on Samsung 0.18 um CMOS technology. The synthesis result shows that the proposed hardware can operate at 62.5MHz. In this case, it can process about 88 QCIF video frames per second. The hardware is being used as a core module when implementing a complete MPEG-4 AVC video encoder chip for real-time multimedia application.