• Korean Journal of Optics and Photonics
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• v.12 no.2
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• pp.98-102
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• 2001

To analyze the saturating process of $Cr^{4+}:YAG$ crystal and plastic organic dye as the saturable absorber, we have measured the residual optical losses between a free running and a passive Q-switching mode for various optical densities. The undepleted ground state population density and the saturated transmission of the saturable absorber have been evaluated by the additional optical losses with the increased threshold pump energies between two resonators. ill the passive Q-switching mode, the saturable transmission of saturable absorber is less than the maxrnium saturable transmission due to the undepleted ground state population density. nsity.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.6
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• pp.89-95
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• 2009

A new class of electronically commutated brushless motor, the flux-switching motor(FSM) is gradually emerging in power tools and household appliances especially fan and pump application because of green policy. This motor offers advantages of high-power density and relatively high efficiency compare with induction motor, low cost and simple motor structure compare with bldc motor. This paper presents the principle of the FSM and design of the 12/6 pole FSM drive system for fan application. Finally, test results of the prototype motor are provided to verify a validity of the fan application with TMS320F2812 DSP and inverter.

• Proceedings of the Optical Society of Korea Conference
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• 2000.02a
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• pp.114-115
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• 2000

Halobacterium halobium에서 추출한 Bacteriorhodopsin(bR)을 고분자 물질에 첨가해 박막화하였다. 이 단백질 박막 소자의 photodynamic특성을 이용하여 광 switching system을 구성하였다. 광 switch system은 pump광을 이용해 B상태와 M상태에서 축퇴4광파 혼합방식으로 구성했다. Red, blue, violet 광원을 사용하여 B상태와 M상태 격자를 형성하고 on-off되는 위상공액신호를 측정했다. (중략)

• Journal of Sensor Science and Technology
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• v.32 no.6
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• pp.432-440
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• 2023

This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 V_PP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm². Experimental evaluations showed a 0.59 µV_RMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.5
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• pp.2414-2419
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• 2012

This paper presents an optimal operation control method for energy saving in the water reuse pumping system. A predictive horizon switching strategy is proposed to implement an optimal operation control and a linear programming (LP) algorithm is used to solve optimal problems in each time step. Energy costs are calculated for electricity on both TOU in the light, heavy, and maximum load time period and peak charges. The optimal operation in water reuse pumping systems is determined to reduce the TOU and peak costs. The simulation results show a power energy saving for water reuse pumping systems and power stability improvement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.23-30
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• 2000

The performance of two types of surface reflecting all-optical switches with InGaAs/InAlAs multiple quantum wells are investigated. The absorption spectra and the refractive index changes of the quantum well are calculated for various pump and probe beam intensities and device conditions. From theses results, on ON/OFF ratio and switching speed of the two switches are compared. It is shown that the switch using DBR has higher ON/OFF ratio and higher switching speed than the switch without DBR.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.499-500
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• 2006

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.231-238
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• 2013

This paper describes a DC-DC converter IC for Flat Panel Displays. In case of operate LCD devices various type of DC supply voltage is needed. This device can convert DC voltage from 6~14[V] single supply to -5[V], 15[V], 23[V], and 3.3[V] DC supplies. In order to meet current and voltage specification considered different type of DC-DC converter circuits. In this work a negative charge pump DC-DC converter(-5V), a positive charge pump DC-DC converter(15V), a switching Type Boost DC-DC converter(23V) and a buck DC-DC converter(3.3V). And a oscillator, a thermal shut down circuit, level shift circuits, a bandgap reference circuits are designed. This device has been designed in a 0.35[${\mu}m$] triple-well, double poly, double metal 30[V] CMOS process. The designed circuit is simulated and this one chip product could be applicable for flat panel displays.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.1
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• pp.1-7
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• 1998

Due to the increase in capacity of auxiliary machinery in power plant, the importance of energy saving has been greatly emphasized. If the speed of fans or pumps is controlled in accordance with the variation of load, large electric energy can be saved. Large capacity inverter, 2MVA GTO inverter, has been developed by operating two of 1MVA unit inverters in parallel. The parallel operation of the unit inverter is accomplished through two output transformers of which the secondary windings are connected in series. The system is composed of one control cubicle, one rectifier cubicle and 2 unit inverter cubicles. This inverter system was applied to the sea water lift pump(SLP) driven by a 6.6KV 1500KW induction motor in Seo-Inchon power plant to save the electric energy. The parallel operation of inverters by 180 degrees apart in switching frequency helps to reduce the harmonic components.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2366-2373
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• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.