• Proceedings of the KIEE Conference
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• 2002.06a
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• pp.55-59
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• 2002

This paper presents a novel three-phase current-fed Pulse Width Modulation converter with switched capacitor type resonant DC link commutation circuit operating PWM pattern strategy under a design consideration of low-pass filter, which can operate on the basis of the principle of zero current soft switching commutation. In the first place, the steady state operating principle of this converter with a new resonant DC link snubber circuit is described in connection with the equivalent operation circuit, together with the practical design procedure of the switched-capacitor type resonant DC link circuit is discussed from a theoretical viewpoint on the basis of a design example for high-power applications. The actively delayed time correction method to compensate distorted currents due to a relatively long resonant commutation time is newly implemented in the open loop control scheme so as to acquire the new optimum PWM pattern. Finally, the experiment of set-up in laboratory system of this converter is concretely demonstrated herein to confirm a zero current soft-switching commutation of this converter. The comparative evaluations between current -fed hard switching PWM and soft-switching PWM converters are carried out from a viewpoint of their PWM converter characteristics.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.2
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• pp.49-55
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• 2003

This paper presents a novel three-phase current-fed Pulse Width Modulation converter with switched capacitor type resonant DC link commutation circuit operating PWM pattern strategy under a design consideration of low-pass filter, which can operate on the basis of the principle of zero current soft switching commutation. In the first place, the steady state operating principle of this converter with a new resonant DC link snubber circuit is described in connection with the equivalent operation circuit, together with the practical design procedure of the switched-capacitor type resonant DC link circuit is discussed from a theoretical viewpoint on the basis of a design example for high-power applications. The actively delayed time correction method to compensate distorted currents due to a relatively long resonant commutation time is newly implemented in the open loop control scheme so as to acquire the new optimum PWM pattern. Finally, the experiment of set-up in laboratory system of this converter is concretely demonstrated herein to confirm a zero current soft-switching commutation of this converter. The comparative evaluations between current-fed hard switching PWM and soft-switching PWM converters are carried out from a viewpoint of their PWM converter characteristics.

• Journal of Power Electronics
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• v.15 no.2
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• pp.504-517
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• 2015

This paper presents a novel switching voltage model and an offset-based pulse width modulation (PWM) scheme for multilevel inverters with unbalanced DC sources. The switching voltage model under a DC voltage imbalance will be formulated in general form for multilevel neutral-point-clamped topologies. Analysis of the reference switching voltages from active and non-active switching voltage components in abc coordinates can enable voltage implementation for an unbalanced DC-source condition. Offset voltage is introduced as an indispensable variable in the switching voltage model for multilevel voltage-source inverters. The PWM performance is controlled through the design of two offset components in a subsequence. One main offset may refer to the common mode voltage, and the other offset restricts its effect on the quality of PWM control in related DC levels. The PWM quality can be improved as the switching loss is reduced in a discontinuous PWM mode by setting the local offset, which is related to the load currents. The validity of the proposed algorithm is verified by experimental results.

• Proceedings of the KIPE Conference
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• 2008.10a
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• pp.16-18
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• 2008

A novel general direct duty ratio pulse width modulation strategy is proposed to modulate matrix converters. By using average concept over one switching period, the modulation algorithm and the required equations are derived to synthesize the desired output voltage and to achieve the controlled input power factor. The proposed method use continuous carrier and the predetermined duty ratio signal for directly generating gating signals an thus is named "direct duty ratio PWM(DDPWM)". The feasibility and validity of the proposed strategy are verified by experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.3
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• pp.239-246
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• 2015

A novel control method of a three-phase PWM inverter with LC filter is proposed. The transfer function of LC filter is the same as that of second-order low pass filter(LPF), which has a zero damping ratio. A simple method of implementing second-order LPF with damping ratio is to add a resistor in an LC circuit. However, in a real power system, adopting damping resistors is impractical because it results in losses proportional to the square of the current flowing through the resistors. Instead of inserting resistors, the proposed control strategy utilizes the measured capacitor voltages to control the oscillation of LC circuit. The overall transfer function of the proposed method is the same as a second-order LPF, and its damping ratio is controllable via control variables. The current controller can have overshoots caused by LC filter. Improved current controller is implemented by an equivalent second-order of LC filter. A 7.5 kVA PWM converter and a PWM inverter with a 5.5 kW induction motor are set up to verify the proposed control algorithm. Test waveforms are also presented to verify the proposed LC filter control algorithm.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.944-951
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• 2015

Pulse Width Modulation (PWM) techniques are increasingly employed for PWM inverter fed induction motor drive. Among various popular PWM methods used, Selective Harmonic Elimination PWM (SHEPWM) has been widely accepted for its better harmonic elimination capability. In addition, using SHEPWM, it is also possible to maintain better voltage regulation. Hence, in this paper, an attempt has been made to apply Bacterial Foraging Algorithm (BFA) for solving selective harmonic elimination problem. The problem of voltage harmonic elimination together with output voltage regulation is drafted as an optimization task and the solution is sought through proposed method. For performance comparison of BFA, the results obtained are compared with other techniques such as derivative based Newton-Raphson method, and Genetic Algorithm. From the comparison, it can be observed that BFA based approach yields better results. Further, it provides superior convergence, reduced computational burden, and guaranteed global optima. The simulation results are validated through experimental findings.

• Journal of Power Electronics
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• v.18 no.3
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• pp.789-801
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• 2018

Model predictive direct power control (MPDPC) is a widely recognized high-performance control strategy for a three-phase grid-connected pulse width modulation (PWM) rectifier. Unlike those of conventional grid-connected PWM rectifiers, the active and reactive powers of permanent magnet synchronous generator (PMSG)-connected PWM rectifiers, which are used in electromagnetic transmitters, cannot be calculated as the product of voltage and current because the back electromotive force (EMF) of the generator cannot be measured directly. In this study, the predictive power model of the rectifier is obtained by analyzing the relationship among flux, back EMF, active/reactive power, converter voltage, and stator current of the generator. The concept of duty cycle control in the proposed MPDPC is introduced by allocating a fraction of the control period for a nonzero vector and rest time for a zero vector. When nonzero vectors and their duration in the predefined cost function are simultaneously evaluated, the global power ripple minimization is obtained. Simulation and experimental results prove that the proposed MPDPC strategy with duty cycle control for the PMSG-connected PWM rectifier can achieve better control performance than the conventional MPDPC-SVM with grid-connected PWM rectifier.

• Journal of Power Electronics
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• v.15 no.2
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• pp.378-388
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• 2015

This paper proposes a pulse width modulation (PWM)-based sliding mode controller (SMC) for a full-bridge DC-DC converter that can eliminate static output voltage error. Hysteretic SMC in DC-DC converter does not have a fixed switching frequency, and applying hysteretic SMC to full-bridge converters is difficult. Fixed-frequency SMC, which is also called PWM-based SMC, based on equivalent control overcomes these shortcomings. However, the controller order reduction in equivalent control in PWM-based SMC causes static output voltage error. To resolve this issue, an integral item is added to the PWM-based SMC. Sliding mode coefficients are designed by applying a standard second-order system to the sliding mode surface. The effect of adding an integral item on the controller is analyzed, and an integral coefficient design method is proposed. Experiment results on a three-level full-bridge DC-DC converter verify the control scheme and design method proposed in this paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.652-654
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• 2016

This paper shows the Design and implementation of sinusoidal BLDC motor drive logic using SVPWM method with FPGA. Sinusoidal BLDC motor driver logic consists of sine-wave PWM generator, dead-time and lead angle control logic. PWM generator logic is designed using SVPWM method for increase of 15.5% linear domain than general sine-wave PWM. This logic is verified and implemented using Spartan-6 FPGA Board. Test results show that THD(Total Harmonic Distortion) of motor-driving current is 19.2% and rotor position resolution is 1.6 degree.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.371-378
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• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.