• ETRI Journal
• /
• v.37 no.6
• /
• pp.1120-1128
• /
• 2015

We propose a pseudo optical N-level pulse-amplitude modulation (PO PAM-N) signal using a few externally-modulated lasers (EMLs) operating at different wavelengths, which is suitable for upgrading the transmission speed over an optical link of < 10 km single-mode fiber with low-cost components. To compare a PO PAM-N signal with that of a standard optical PAM-N signal, we perform experiments for evaluating the performance of a 51.56-Gb/s PO PAM-4 signal and standard 51.56-Gb/s optical PAM-4 signal. The receiver sensitivity (at $BER=10^{-5}$) of the PO PAM-4 signal is 1.5 dB better than the receiver sensitivity of a standard optical PAM-4 signal. We also investigate the feasibility of PO PAM-N (N = 4, 8, and 16) signals operating at 103.12 Gb/s, considering relative intensity noise, timing jitter, extinction ratio (ER) of EMLs, and dispersion. From the results, a PO PAM-8 signal performs better than PO PAM-4 and PO PAM-16 signals at 103.12 Gb/s. Finally, we suggest a timing control method to suppress the effect of dispersion in a PO PAM-N signal. We show that the tolerance to dispersion of a 103.12-Gb/s PO PAM-8 signal can be improved to ${\pm}40ps/nm$ by applying a proposed scheme.

• Journal of international Conference on Electrical Machines and Systems
• /
• v.1 no.3
• /
• pp.372-378
• /
• 2012

This paper deals with a 3-phase voltage disturbance generator for a performance test of custom power devices such as dynamic voltage restorers (DVR), dynamic uninterruptable power supplies (UPS), etc. The operating principle of the proposed circuit is described in each mode of voltage sag, swell, outage, and unbalance. The main components of the proposed disturbance generator are silicone controlled rectifier (SCR) thyristors, variable autotransformers, and transformers. Therefore, the disturbance generator can be implemented with a considerably low cost compared to the conventional pulse width modified (PWM) inverter and converter type generators. Furthermore, it has good features of high reliability with simple structure, high efficiency caused by no PWM switching of the SCR thyristors, and easy control with a wide variation range. To verify the validity of the proposed scheme, simulations and experiments are carried out.

• IEIE Transactions on Smart Processing and Computing
• /
• v.2 no.4
• /
• pp.248-254
• /
• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.13 no.6
• /
• pp.1180-1187
• /
• 2010

In the last decade, hydrogen peroxide has received renewed interest as a green propellant which is non-toxic, environmentally clean and relatively easy to handle. This study was performed to acquire the design technique and combustion performance of a 200N bi-propellant engine using hydrogen peroxide and kerosene. The engine which used a catalytic ignition method was designed and cold flow tests were carried out to investigate atomization characteristics. Combustion tests including a pulse mode operation were performed to investigate the combustion performance on various O/F ratios. The results showed that the combustion efficiency and the repeatability of the engine performance were enough to use as an essential database for the development of a high performance engine.

• Journal of information and communication convergence engineering
• /
• v.9 no.1
• /
• pp.32-37
• /
• 2011

In dispersion management (DM) and optical phase conjugation applied into optical transmission links with multi fiber spans for minimizing the impact of nonlinearity and group velocity (GVD), implementation possibility of DM using only one fiber span for pre- or postcompensation was assessed as a function of duty cycle of RZ pulse and residual dispersion per span (RDPS). It is confirmed that DM with optimal net residual dispersion (NRD) controlled by only one fiber span could be sufficiently applied into optical transmission links, though optimal NRD is more increased than that in transmission links with the general DM scheme of pre- and postcompensation. Thus, it is expected that optical transmission system is simply designed and implemented by applying the proposed DM scheme into real optical transmission links. Also, it is confirmed that the advantageous duty cycle of RZ is 0.5 and RDPS is setting to be small value for the effective transmitting wide signal wavelength range in optical links with optimal NRD controlled by only one fiber span.

• Journal of Electrical Engineering and Technology
• /
• v.8 no.2
• /
• pp.295-303
• /
• 2013

This paper reports an investigation of pulse width modulation (PWM) techniques for two-phase brushless DC (BLDC) motors fed by a two-phase eight-switch inverter in a fan application. The three-phase BLDC motor is widely applied in industry; however, a lower-cost two-phase BLDC motor and drive circuit has been greatly in demand in recent years. In this paper, we introduce a mathematical model of the two-phase BLDC motor with sinusoidal back electromotive forces (EMFs) based on traditional three-phase BLDC motors. To simplify the drive algorithm and speed up its application, we analyze the principle of block commutation for a two-phase BLDC motor drive in the 180-electrical-degree conduction mode, and we further propose five PWM schemes to improve the commutation performance of the two-phase BLDC drive. The effectiveness of the proposed PWM methods is verified through experiments.

• Journal of Power Electronics
• /
• v.16 no.3
• /
• pp.840-848
• /
• 2016

A primary-side regulation AC-DC converter operating in the PFM (Pulse Frequency Modulation) mode with a high precision output current is designed, which applies a novel inductance compensation technique to improve the precision of the output current, which reduces the bad impact of the large tolerance of the transformer primary side inductance in the same batch. In this paper, the output current is regulated by the OSC charging current, which is controlled by a CC (constant current) controller. Meanwhile, for different primary inductors, the inductance compensation module adjusts the OSC charging current finely to improve the accuracy of the output current. The operation principle and design of the CC controller and the inductance compensation module are analyzed and illustrated herein. The control chip is implemented based on a TSMC 0.35μm 5V/40V BCD process, and a 12V/1.1A prototype has been built to verify the proposed control method. The deviation of the output current is within ±3% and the variation of the output current is less than 1% when the inductances of the primary windings vary by 10%.

• Information and Communications Magazine
• /
• v.32 no.8
• /
• pp.62-68
• /
• 2015

본고에서는 차세대 보안통신 기술로 주목 받고 있는 양자암호시스템의 핵심 모듈인 단일광자 검출기의 최신 연구동향과 KIST 연구개발 내용에 대해 기술한다. 현재 상용화 수준으로까지 발전한 유선 양자암호 시스템에서는 성능, 소형화, 가격 등의 장점으로 인해 주로 InGaAs/InP avalanche photo diode (APD)를 이용한 단일광자검출기가 사용되고 있다. 유선 양자암호에서 사용하는 1550nm 통신 파장대의 단일광자가 갖는 에너지는 0.8 eV로 매우 미약한 수준이기 때문에 신호 검출을 위해 APD소자를 내부 증폭 이득이 무한대인 가이거모드(Geiger mode)에서 동작시킨다. 매우 높은 증폭비는 신호 검출뿐만 아니라 노이즈에도 동일하게 영향을 미치기 때문에 주변환경 노이즈에 의한 검출기 오동작 문제가 심각하게 발생한다. 따라서 단일광자검출기 구현에서 가장 중요한 기술은 소자 및 검출기 모듈에서 발생하는 노이즈의 영향을 최소화 시켜주는 것이다. 전세계적으로 검출기의 대표적인 노이즈인 after pulse를 저감 시키기 위한 연구가 매우 활발히 이루어지고 있는데 대표적으로 self-differencing, auxiliary signal, integrating, double balanced 등의 방법이 제시되고 있다. 본고에서는 각각의 최신 기술들에 대한 비교 분석 및 이를 바탕으로 현재 KIST에서 진행하고 있는 양자암호시스템을 위한 단일광자검출기 기술 개발에 대해 서술한다.

• Journal of the Korean Society of Manufacturing Technology Engineers
• /
• v.21 no.1
• /
• pp.102-108
• /
• 2012

A study of terahertz waves (T-ray) was made for the nondestructive evaluation of FRP (Fiber reinforced plastics) composite materials. The to-be-used systems were time domain spectroscopy (TDS) and continuous wave (CW). The composite materials investigated include both turbine blades of wind energy (non-conducting polymeric composites) and conducting carbon fiber composites. Terahertz signals in the TDS mode resembles that of ultrasound; however, unlike ultrasound, a terahertz pulse was not able to detect a material with conductivity. This was demonstrated in CFRP (Carbon fiber reinforced plastics) laminates. Refractive index (n) was defined as one of mechanical properties; so a method was solved in order solve the "n" in the material with the cut parts of the turbine blades of wind energy. The defects and anomalies investigated by terahertz radiation were foreign material inclusions and simulated disband. Especially, it is found that the T-ray went through the turbine blade with greater thickness (about 90mm).

• ETRI Journal
• /
• v.33 no.5
• /
• pp.752-758
• /
• 2011

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.