• The Journal of the Korea institute of electronic communication sciences
• /
• v.14 no.1
• /
• pp.87-96
• /
• 2019

Flexible organic light-emitting diode (OLED) displays with organic thin-film transistors (OTFTs) backplanes have been studied. A gate driver is required to drive the OLED display. The gate driver is integrated into the panel to reduce the manufacturing cost of the display panel and to simplify the module structure using fabrication methods based on low-temperature, low-cost, and large-area printing processes. In this paper, pseudo complementary metal oxide semiconductor (CMOS) logic gates are implemented using OTFTs for the gate driver integrated in the flexible OLED display. The pseudo CMOS inverter and NAND gates are designed and fabricated on a flexible plastic substrate using inkjet-printed OTFTs and the same process as the display. Moreover, the operation of the logic gates is confirmed by measurement. The measurement results show that the pseudo CMOS inverter can operate at input signal frequencies up to 1 kHz, indicating the possibility of the gate driver being integrated in the flexible OLED display.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.5
• /
• pp.82-89
• /
• 1993

In this paper, we proposed the autonomous algorithm of pseudo-exhaustive testing for the multi-level combinational logic circuits. For the processing of shared-circuit that existed in each cone-circuit when it backtracked the path from PO to PI of CUT at the conventional verification testing, the dependent relation of PI-P0 is presented by a dependence matrix so it easily partitioned the sub-circuits for the pseudo-exhaustive testing. The test pattern of sub-circuit's C-inputs is generated using a binary counter and the test pattern of I-inputs is synthesized using a singular cover and consistency operation. Thus, according to the test patterns presented with the recipe cube, the number of test pattrens are reduced and it is possible to test concurrently each other subcircuits. The proposed algorithm treated CUT's net-list to the source file and was batch processed from the sub-circuit partitioning to the test pattern generation. It is shown that the range of reduced ration of generated pseudo-exhaustive test pattern exhibits from 85.4% to 95.8% when the average PI-dependency of ISACS bench mark circuits is 69.4%.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• v.13 no.3
• /
• pp.208-214
• /
• 2013

Bandler and Kohout investigated the solvability of fuzzy relation equations with inf-implication compositions in complete lattices. Perfilieva and Noskova investigated the solvability of fuzzy relation equations with inf-implication compositions in BL-algebras. In this paper, we investigate various solutions of fuzzy relation equations with inf-implication compositions in pseudo BL-algebras.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• v.9 no.1
• /
• pp.30-35
• /
• 2009

We investigate the properties of fuzzy relations, metrics and $\bigodot$-equivalence relation on a stsc quantale lattice L and a commutative cqm-lattice. In particular, pseudo-(quasi-) metrics induce $\bigodot$-(quasi)-equivalence relations.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.3
• /
• pp.176- 184
• /
• 2010

A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 mW. The area of the DEMUX core is $29\;{\times}\;40\;{\mu}m^2$. The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 mW. The area of the MUX core is $30\;{\times}\;18\;{\mu}m^2$. The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-to-rail, and a low $V_{dd}$. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.

• 제어로봇시스템학회:학술대회논문집
• /
• 2001.10a
• /
• pp.93.1-93
• /
• 2001

An evolutionary approach for the design of Fuzzy Logic Systems(FLSs) is proposed. Membership functions(MFs) in Takagi-Sugeno type fuzzy logic system is optimized through evolutionary process. Output singleton values are obtained through pseudo-inverse method. The proposed technique is unique for that, to prevent overfilling phenomenon, limited-level RBF membership functions are used and the new fitness function is invented. To show the effectiveness of the proposed method, some simulations results on model identification are given.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.12
• /
• pp.229-240
• /
• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• Korean Journal of Logic
• /
• v.21 no.1
• /
• pp.39-57
• /
• 2018

This paper deals with non-algebraic Kripke-style semantics, i.e, set-theoretical Kripke-style semantics, for weakening-free non-commutative fuzzy logics. We first recall an extension of the pseudo-uninorm based fuzzy logic HpsUL, $CnHpsUL^*$. We next introduce set-theoretical Kripke-style semantics for it.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.3
• /
• pp.341-352
• /
• 2012

This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven and low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce operating power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18 2m CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1 pJ/cycle when working at the frequency of 403 MHz, which is only 36% of PE with the conventional static CMOS gates. The measurement results show that the test chip can work as high as 609 MHz with the energy dissipation of 2.1 pJ/cycle.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• v.12 no.1
• /
• pp.15-19
• /
• 2012

A Domain Dictionary generation algorithm based on pseudo feedback model is presented in this paper. This algorithm can increase the precision of domain dictionary generation algorithm. The generation of Domain Dictionary is regarded as a domain term retrieval process: Assume that top N strings in the original retrieval result set are relevant to C, append these strings into the dictionary, retrieval again. Iterate the process until a predefined number of domain terms have been generated. Experiments upon corpus show that the precision of pseudo feedback model based algorithm is much higher than existing algorithms.