• Journal of Power Electronics
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• v.10 no.1
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• pp.65-71
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• 2010

This paper presents the design and implementation of voltage source inverter type SVPWM based speed control of an induction motor using a fuzzy PI controller. This scheme enables us to adjust the speed of the motor by controlling the frequency and amplitude of the stator voltage; the ratio of the stator voltage to the frequency should be kept constant. A model of the fuzzy control system is implemented in real time with a Xilinx FPGA XC3S 400E. It is introduced to maintain a constant speed to when the load varies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4C
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• pp.379-388
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• 2007

In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improve the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times.

• Journal of Power Electronics
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• v.16 no.1
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• pp.190-204
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• 2016

An active front end (AFE) is required for a three-phase induction motor (IM) fed by a voltage source inverter (VSI), because of the increasing need to derive quality current from the utility end without sacrificing the power factor (PF). This study investigates a proportional-plus-integral (PI) controller based AFE topology that uses a super-lift converter (SLC). The significance of the proposed SLC, which converts rectified AC supply to geometrically proceed ripple-free DC supply, is explained. Variations in several power quality parameters in the intended IM drive for 0% and 100% loading conditions are demonstrated. A simulation is conducted by using MATLAB/Simulink software, and a prototype is built with a field programmable gate array (FPGA) Spartan-6 processor. Simulation results are correlated with the experimental results obtained from a 0.5 HP IM drive prototype with speed feedback and a voltage/frequency (V/f) control strategy. The proposed AFE topology using SLC is suitable for three-phase IM drives, considering the supply end PF, the DC-link voltage and current, the total harmonic distortion (THD) in supply current, and the speed response of IM.

• Journal of Power Electronics
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• v.15 no.1
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• pp.131-145
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• 2015

The voltage-source inverters (VSI) supplying a motor drive are prone to open transistor faults. To address this issue in fault-tolerant drives applicable to electric vehicles, a new open transistor fault diagnosis (FD) method is presented in this paper. According to the proposed method, in order to define the FD index, the phase angle of the converter output current is estimated by a simple trigonometric function. The proposed FD method is adaptable, simple, capable of detecting multiple open switch faults and robust to load operational variations. Keeping the FD in mind as a mandatory part of the fault tolerant control algorithm, the FD block is applied to a five-phase converter supplying a multiphase fault-tolerant PM motor drive with non-sinusoidal unbalanced current waveforms. To investigate the performance of the FD technique, the fault-tolerant sliding mode control (SMC) of a five-phase brushless direct current (BLDC) motor is developed in this paper with the embedded FD block. Once the theory is explained, experimental waveforms are obtained from a five-phase BLDC motor to show the effectiveness of the proposed FD method. The FD algorithm is implemented on a field programmable gate array (FPGA).

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.34-39
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• 2016

A low-voltage, low-power analog front-end IC for neural recording implant devices is presented. The proposed IC consists of a low-noise neural amplifier and a programmable active bandpass filter to process neural signals residing in the band of 1 Hz to 5 kHz. The neural amplifier is based on a source-degenerated folded-cascode operational transconductance amplifier (OTA) for good noise performance while the following bandpass filter utilizes a low-power current-mirror based OTA with programmable high-pass cutoff frequencies from 1 Hz to 300 Hz and low-pass cutoff frequencies from 300 Hz to 8 kHz. The total recording analog front-end provides 53.1 dB of voltage gain, $4.68{\mu}Vrms$ of integrated input referred noise within 1 Hz to 10 kHz, and noise efficiency factor of 3.67. The IC is designed using $18-{\mu}m$ CMOS process and consumes a total of $3.2{\mu}W$ at 1-V supply voltage. The layout area of the IC is $0.19 mm^2$.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06b
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• pp.394-396
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• 2006

A blooming area of processor design is represented by scalable computing fabric. As the structure of the processors developed using seal-able computing fabric evolved from simple programmable units to processors supporting change of flow instructions and function calls, an increasing interest is in developing the compiling technology that will allow us to harness not only the full power of their hardware but also to target multiple architectures. In this paper we present the front-end of a generic compiler, able to accept a various source languages and transform them in a common intermediate representation.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1535-1544
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• 2017

Advances in FPGA technology have enabled fast real-time simulation of power converters, filters and loads. FPGA based HIL (Hardware-In-the-Loop) simulators have revolutionized control hardware and software development for power electronics. Common time step sizes in the order of 100ns are sufficient for simulating switching frequency current and voltage ripples. In order to keep the time step as small as possible, ideal switching function models are often used to simulate the phase legs. This often produces inferior results when simulating the discontinuous conduction mode (DCM) and disabled operational states. Therefore, the corresponding measurement and protection units cannot be tested properly. This paper describes a new solution for this problem utilizing a discrete-time PI controller. The PI controller simulates the proper DC and low frequency AC components of the phase leg voltage during disabled operation. It also retains the advantage of fast real-time execution of switch-based models when an accurate simulation of high frequency junction capacitor oscillations is not necessary.

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.2018-2030
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• 2015

A two stage ac drive configuration consisting of a single-phase line commutated rectifier and a three-phase voltage source inverter (VSI) is very common in low and medium power applications. The deterministic pulse width modulation (PWM) methods like sinusoidal PWM (SPWM) could not be considered as an ideal choice for modern drives since they result mechanical vibration and acoustic noise, and limit the application scope. This is due to the incapability of the deterministic PWM strategies in sprawling the harmonic power. The random PWM (RPWM) approaches could solve this issue by creating continuous harmonic profile instead of discrete clusters of dominant harmonics. Insufficient filtering at dc link results in the amplitude distortion of the input dc voltage to the VSI and has the most significant impact on the spectral errors (difference between theoretical and practical spectra). It is obvious that the sprawling effect of RPWM undoubtedly influenced by input fluctuation and the discrete harmonic clusters may reappear. The influence of dc link fluctuation on harmonics and their spreading effect in the VSI remains invalidated. A case study is done with four different filter capacitor values in this paper and results are compared with the constant dc input operation. This paper also proposes an ingenious RPWM, a ripple dosed sinusoidal reference-random carrier PWM (RDSRRCPWM), which has the innate capacity of suppressing the effect of input fluctuation in the output than the other modern PWM methods. MATLAB based simulation study reveals the fundamental component, total harmonic distortion (THD) and harmonic spread factor (HSF) for various modulation indices. The non-ideal dc link is managed well with the developed RDSRRCPWM applied to the VSI and tested in a proto type VSI using the field programmable gate array (FPGA).

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.3
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• pp.273-277
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• 2016

In this paper, we deals with the digitization of high frequency sine wave power supply using power source of high frequency surgical equipment and RF device. High frequency surgical equipment has been using commonly on medical surgery because of its merits such as programmable depth of incision, availability of incision and coagulation in the same device, increasing the usability on surgical side. However, the core part of the device is consists of vacuum tubes which are expensive, not ease to use and must be imported, therefore it is inevitable of high prices, forces to develop the fully digitized alternative technology. The fully digitized high frequency sine wave power supply for surgical device is proposed and verified by experimental results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.4
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• pp.326-330
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• 2020

Small-scale production control systems for smart manufacturing are becoming increasingly necessary as the manufacturing industry seeks to maximize manufacturing efficiency as the demand for customized product production increases. Correspondingly, the development of an embedded system to realize this capability is becoming important. In this study, we developed an embedded system based on an open source system that is cheaper than a widely applied programmable logic controller (PLC)-based production control system that is easier to install, configure, and process than a conventional relay control panel. This embedded system is system is based on a low-power, high-performance Cortex M4 processor and can be applied to smart manufacturing. It is designed to improve the development environment and compatibility of existing PLCs, control small-scale production systems, and enable data collection through heterogeneous communication. The real-time response characteristics were confirmed through an operation test for input/output control and data collection, and it was confirmed that they can be used in industrial sites.