• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.1
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• pp.48-53
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• 2000

The novel integration method with programmable high-pass filter is suggested in order to solve the problem of integration for stator flux estimation in a stator flux oriented direct vector controlled induction motor drive system. The dc offset in a pure integrator is eliminated using high-pass filter with fixed time constant, and then time constant of programmable high-pass filter is controlled with a inverter frequency for integration in a wide frequency range, considering phase lag and attenuation due to both the hardware low-pass filter and high-pass filter. The proposed method is verified with the experimental results implemented by 32-bit DSP.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.1
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• pp.35-41
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• 2014

This paper presents a design method of programmable low pass filter(PLPF) which reduce an estimation error of a zero crossing point(ZCP) for a high speed brushless DC(BLDC) motor drive. BLDC motor sensorless drive is possible by estimation of ZCP. The ZCP estimated by detecting a change of back-EMF polarity has the estimation error because noises exist on the measured back-EMF. Therefore a calculated commutation timing using the ZCP is inaccurate. And the inexact commutation timing leads to ripples of 3-phase current and degradation of drive performance. This paper proposes the design method of the PLPF to overcome these problems. First, a speed calculated a inaccurate period of the ZCP is analyzed in the frequency domain. Then, the PLPF that has varying cut-off frequency according to change of the speed is designed on the frequency analysis result. The proposed method is verified by the experiment.

• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.6
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• pp.23-30
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• 2014

This paper proposes a dead time compensation method for an AC motor drive using phase current polarity information which is detected based on a digital programmable low-pass filter (PLPF). The polarity detection using the PLPF is an alternative solution of a conventional method which uses a general low-pass filter (LPF) and hysteresis bands in order to avoid jittering due to noises. The PLPF not only adjusts its cutoff frequency according to the synchronous frequency of AC motors but also eliminates a gain attenuation and phase delay which are main problems of the general LPF. Through the PLPF, a fundamental component signal without gain and phase distortions is extracted from the measured raw current signal with noise. By use of the fundamental component, the polarity of current is effectively detected by reducing the hysteresis band. Finally, the proposed method compensates the dead time effects by adding or subtracting average voltage value to voltage references of the controller according to the detected current polarity information. The proposed compensation method is experimentally verified by compared with the conventional method.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.10
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• pp.74-81
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• 2006

This paper proposes the sensorless vector control scheme of a Non-salient permanent-magnet synchronous motor (SPMSM) using programmable low pass filter (PLPF) to estimate a stator flux with the information of a rotor position and speed. The sesorless vector control of PMSM using PLPF can solves the dc drift problem associated with a pure integrator and a LPF. Also, the PLPF has the phase and gain compensator to estimate exactly rotor position and speed. Therefore, the information of a position and speed is exactly estimated because the drift and offset problems are solved by the PLPF. The experimental results show good performance over the 10[%] of the rated speed and under load condition.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.282-291
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• 2010

This paper presents a full-CMOS transmitter and receiver for VDSL2 systems. The transmitter part consists of the low-pass filter, programmable gain amplifier (PGA) and 14-bit DAC. The receiver part consists of the low-pass filter, variable gain amplifier (VGA), and 13-bit ADC. The low pass filter and PGA are designed to support the variable data rate. The RC bank sharing architecture for the low pass filter has reduced the chip size significantly. And, the 80 Msps, high resolution DAC and ADC are integrated to guarantee the SNR. Also, the transmitter and receiver are designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. The chip is implemented in 0.25 ${\mu}m$ CMOS technology and the die area is 5 mm $\times$ 5 mm. The spurious free dynamic range (SFDR) and SNR of the transmitter and receiver are 67.5 dB and 41 dB, respectively. The power consumption of the transmitter and receiver are 160 mW and 250 mW from the supply voltage of 2.5 V, respectively.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.411-412
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• 2012

본 논문은 유도 전동기 센서리스 제어를 위해 자속 추정기로 사용되는 Programmable low-pass filter (PLPF)의 문제점 분석과 그 해결방안에 관한 연구이다. 기존의 PLPF는 추정된 동기 각속도를 극점으로 사용하고 실제 동기 각속도가 추정 값과 동일하다는 가정하에 순수 적분기와의 위상과 크기 오차를 보상한다. 하지만 추정 동기 각속도가 실제 값과 같지 않다면 이때 얻어진 크기와 위상 보상은 적절하지 않게 되고, 결과적으로 PLPF는 순수적분 기능을 제대로 수행할 수 없게 된다. 본 논문은 PLPF의 문제점을 극복하고자 동기 각속도 오차가 고정자 자속의 위상 지연 오차와 비례함을 분석하고, 이를 통하여 동기 각속도 오차를 보상하는 방법을 제안하였다. 제안한 방법의 타당성은 실험을 통하여 증명되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.682-686
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• 2016

A fully differential RC calibrator for accurate cut-off frequency of a programmable channel selection filter is proposed. The proposed RC calibrator consists of an RC timer, clock generator, synchronous counter, digital comparator, and control block. To verify the proposed RC calibrator, a six-order Chebyshev programmable low-pass filter with adjustable 3 dB cut-off frequency, which is controlled by the proposed RC calibrator, was implemented in a $0.18-{\mu}m$ CMOS technology. The channel selection filter with the proposed RC calibrator draws 1.8 mA from a 1.8 V supply voltage and the measured 3 dB cut-off frequencies of the channel selection LPF is controlled accurately by the RC calibrator.

• Journal of Power Electronics
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• v.6 no.3
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• pp.235-244
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• 2006

Recently, speed sensorless vector control for synchronous reluctance motors (SYRMs) has deserved attention because of its advantages. Although rotor angle calculation using flux estimation is a straightforward approach, the DC offset can cause an increasing pure integrator error in this estimator. In addition, this method is affected by parameter fluctuation. In this paper, to control the motor at the low speed region, a modified programmable cascaded low pass filter (MPCPLF) with sensorless online parameter identification based on a block pulse function is proposed. The use of the MPCLPF is suggested because in programmable, cascade low pass filters (PCLPF), which previously have been applied to induction motors, the drift increases vastly wl)en motor speed decreases. Parameter identification is also used because it does not depend on estimation accuracy and can solve parameter fluctuation effects. Thus, sensorless speed control in the low speed region is possible. The experimental system includes a PC-based control with real time Linux and an ALTERA Complex Programmable Logic Device (CPLD), to acquire data from sensors and to send commands to the system. The experimental results show the proposed method performs well, speed and angle estimation are correct. Also, parameter identification and sensorless vector control are achieved at low speed, as well as, as at high speed.

• Journal of Power Electronics
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• v.15 no.2
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• pp.419-430
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• 2015

Flux estimation is a significant foundation of high-performance control for DC-excited synchronous motor. For almost all flux estimators, such as the flux estimator based on phase locked loop (PLL), DC drift causes fluctuations in flux magnitude. Furthermore, significant dynamic error may be introduced at transient conditions. To overcome these problems, this paper proposes an improved flux estimator for the PLL-based algorithm. Filters based on the generalized integrator are used to avoid flux fluctuation problems caused by the DC drift at the back electromotive force. Programmable low-pass filters are employed to improve the dynamic performance of the flux estimator, and the cutoff frequency of the filter is determined by the dynamic factor. The algorithm is verified by a 960V/1.6MW industrial prototype. Simulation and experimental results show that the proposed estimator can estimate the flux more accurately than the PLL-based algorithm in a cycloconverter-fed DC-excited synchronous machine vector control system.

• ETRI Journal
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• v.42 no.4
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• pp.534-548
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• 2020

This study presents a new architecture for a field programmable analog array (FPAA) for use in low-frequency applications, and a generalized circuit realization method for the implementation of nth-order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA-C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA-C symmetric balanced structure for even/odd-nth-order low-pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90-nm complementary metal-oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low-power designs for implementation of biopotential signal processing systems.