• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.274-277
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• 1999

The paper describes a implementation of space vector pulse-width modulation (SVPWM) voltage source inverter using Field Programmable Gate Array(FPGA) for a induction motor control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QL16X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed FPGA for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance voltage source inverter drives. Simulation and Implementation results are shown to verify the usefulness of FPGA as a Application Specific Integrated Circuit(ASIC) in power electronics applications

• Journal of Power Electronics
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• v.10 no.1
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• pp.65-71
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• 2010

This paper presents the design and implementation of voltage source inverter type SVPWM based speed control of an induction motor using a fuzzy PI controller. This scheme enables us to adjust the speed of the motor by controlling the frequency and amplitude of the stator voltage; the ratio of the stator voltage to the frequency should be kept constant. A model of the fuzzy control system is implemented in real time with a Xilinx FPGA XC3S 400E. It is introduced to maintain a constant speed to when the load varies.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1161-1164
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• 2003

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array(FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.5
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• pp.477-481
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• 2015

Implementation of memristor-based multilayer neural networks and their hardware-based learning architecture is investigated in this paper. Two major functions of neural networks which should be embedded in synapses are programmable memory and analog multiplication. "Memristor", which is a newly developed device, has two such major functions in it. In this paper, multilayer neural networks are implemented with memristors. A Random Weight Change algorithm is adopted and implemented in circuits for its learning. Its hardware-based learning on neural networks is two orders faster than its software counterpart.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.4
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• pp.85-92
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• 1995

A new partitioning algorithm has been developed to implement a large circuit by using multiple field programmable gate array (FPGA) chips. While the conventional partitioning is to minimze the number of nets cut under size constraints, partitioning for multiple FPGAs has several additional constraints so that each partitioned subcircuit can be implemented in a FPGA chip. To obtain satisfactory results under the constraints, the partitioning is performed in two steps whhich are the intial partitioning for global optimization and the iterative partitioning improvements for constraint satisfaction. Experismental results using the MCNC benchmark examples show that our partition method produces better results thatn those of other recent approaches on the average.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.925-928
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• 1999

A multi-channel gas leakage monitoring system was designed and fabricated by using CPLD(complex Programmable Logic .Device) for monitoring and controlling the leakage of natural gas from supplying-pipes under the ground. Fabricated SnO$_2$thick film gas sensor elements were attached on safeguard steel plate of natural gas supplying pipes, and the local monitoring system in this study received the signal from the gas sensors. The monitoring system was implemented by using CPLD chip to reduce the development time and implement simple one chip system. The time division multi-channel system received the input signal from individual gas sensor at one of divided times by multiplexor and signal processed sequentially. The system reduced the size of peripheral circuit resulted in implementation of creditable simple system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.94-97
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• 2007

The desin and implementation of a CMOS analog integrated circuit that provides dual-mode modulations, PWM for active clamp reset converter and PFM for LLC resonant converter, is described. The proposed controller is capable of implementing programmable soft start and current-mode control with compensating ramp for PWM and frequency shifting soft start for PFM. Also it provides delay time for both modes. PWM mode is implemented by active clamp reset converter and PFM mode is implemented by LLC resonant convereter, respectively. The chip is fabricated using the 0.6um high voltage CMOS process.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.1
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• pp.54-59
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• 2002

In the three-axis control of satellites by using on-board actuators, gyros are usually used to measure the attitude angles and angular rates. The gyros are operated by electronic parts and mechanical actuators. The digital components of the electronic parts consist of largely FPGA (Field Programmable Gate Array) as one of the methods for VLSI(Very Large Scale Integrated) circuit design, while the mechanical parts provide output signal directly by mechanical actuation of a spinning rotor. In this research, a mixed mode of gyro is implemented in FGA. In addition to the hardware implementation, the simulation study was conducted by using the SABER for the mixed mode simulator. Results for the practical implementation of the satellite ACS (Attitude Control System) interfaced with the data processing are also presented to validate the FPGA implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.465-468
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• 2001

An objection of this study is to develop a high stable analytic system of radioactive pulses. The proposed system consists of an amplifying circuit with 60dB gain, a programmable power supply unit which can generate DC voltage up to 1, 500V, and a digital signal processor. Pulse height distribution in accordance with pulse counts is important data in analyzing radioactive pulses. In this study, AD convertor (12bit, l00ns) and DSP (TMS 320C31-60) are used to analyze the pulse height, and the analytic system is designed to be operated in PC-networking.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.30-30
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• 2000

In the three axis control of satellite by using reaction wheel and gyro, a Gyro carries out measuring of the attitude angie and the attitude angular velocity. The Gyro is operated by the electronic part and the mechanic actuator. The digital part of the electronic part is consisted of the FPGA (Field Programmable Gate Array), which is one of the methods for designing VLSI (Very Large Scale Integrated Circuit), and the mechanic actuator processes the input/output data by the dynamic model. In the research of the mixed mode of Gyro, the simulation is accomplished by SABER of the mixed mode simulator and the results for the practical implementation of the satellite ACS (Attitude Control System) interfaced with the data processing are proposed.