• Journal of the military operations research society of Korea
• /
• v.22 no.1
• /
• pp.81-96
• /
• 1996

In a relational database environment, partitioning of data is directly concerned with the amount of data that needs to be required in a query or transaction. In this paper, we consider non-overlapping, vertical partitioning. Vertical partitioning algorithm in this paper is composed of two phases. In phase 1, we cluster the attributes with zero-one integer program that maximize affinity among attributes. The result of phase 1 is called 'Initial Fragments'. In phase 2, we modify Initial Fragments that is not directly considered by cost factors, making use of a transaction-based partitioning method. A transaction-based partitioning method is partitioning attributes according to a set of transactions. In this phase we select logical accesses which needs to be required in a transaction as comparison criteria. In phase 2, proposed algorithm consider only small number of modification of Initial Fragments in phase 1. This algorithm is so insensible to number of transactions and of attributes that it can applied to relatively large problems easily.

• The Transactions of the Korea Information Processing Society
• /
• v.13 no.7
• /
• pp.291-298
• /
• 2024

Despite its wide application, cloud computing raises privacy leakage concerns because users should send their private data to the cloud. Homomorphic encryption (HE) can resolve the concerns by allowing cloud servers to compute on encrypted data without decryption. However, due to the huge computation overhead of HE, simply executing an entire cloud program with HE causes significant computation. Manually partitioning the program and applying HE only to the partitioned program for the cloud can reduce the computation overhead. However, the manual code partitioning and HE-transformation are time-consuming and error-prone. This work proposes a new homomorphic encryption enabled annotation-guided code partitioning compiler, called Heapa, for privacy preserving cloud computing. Heapa allows programmers to annotate a program about the code region for cloud computing. Then, Heapa analyzes the annotated program, makes a partition plan with a variable list that requires communication and encryption, and generates a homomorphic encryptionenabled partitioned programs. Moreover, Heapa provides not only two region-level partitioning annotations, but also two instruction-level annotations, thus enabling a fine-grained partitioning and achieving better performance. For six machine learning and deep learning applications, Heapa achieves a 3.61 times geomean performance speedup compared to the non-partitioned cloud computing scheme.

• Preventive Nutrition and Food Science
• /
• v.14 no.4
• /
• pp.310-315
• /
• 2009

The partitioning behavior of the five printing ink solvents in nine lab-made cookies with various sugar and water content at 25${^{\circ}C}$ was studied to find out the presence and effects of interaction between the two ingredients on partitioning behavior in cookies. Solvents were ethyl acetate, hexane, isopropanol, methyl ethyl ketone and hexane. It was observed that the partition coefficient (the solvent concentration in food compared to that in air, Kp) decreased as sugar increased in all case and increased as water content increased for all compounds except toluene. Statistical analysis by the F-test method was used to determine the significance of sugar-water interactions, as well as other single factors on partitioning behavior of each solvent. Sugar content alone had no significant effects, but the crystallinity of sugar, as changed by water content, affected the partitioning behavior of the five solvents significantly. Parameter estimation for each significant factor by SAS program yielded a regression equation, which was used to predict the partitioning behavior in the finished cookie. Kp values from the regression equation could be determined more precisely by applying a correction term for the interaction between sugar and water to the Kp values of each ingredient after baking.

• Proceedings of the Korean Operations and Management Science Society Conference
• /
• 1997.10a
• /
• pp.166-169
• /
• 1997

For parallel processing, the compiler partitions a loaded program into a set of tasks and makes a schedule for the tasks that will minimize parallel processing time for the loaded program. Building an optimal schedule for a given set of partitioned tasks of a program has known to be NP-complete. In this paper we introduce a GA(Genetic Algorithm)-based scheduling method in which a chromosome consists of two parts of a string which decide the number and order of tasks on each processor. An additional computation is used for feasibility constraint in the chromosome. By granularity theory, a partitioned program is categorized into coarse-grain or fine-grain types. There exist good heuristic algorithms for coarse-grain type partitioning. We suggested another GA adaptive to the coarse-grain type partitioning. The infeasibility of chromosome is overcome by the encoding and operators. The number of processors are decided while the GA find the minimum parallel processing time.

• Journal of KIISE
• /
• v.44 no.7
• /
• pp.649-657
• /
• 2017

As the type and purpose of drones become diverse and the number of additional functions is increasing, the role of the corresponding software has increased. Through partitioning and an efficient solving of SWaP(size, weight and power) problems, ARINC 653 can provide reliable software reuse and consolidation regarding avionic systems. ARINC 653 can be more effectively applied to drones, a small unmanned aerial vehicle, in addition to its application with large-scale aircraft. In this paper, to exploit ARINC 653 for a drone flight-control program, an intra-partition communication system is implemented through an extension of the layered ARINC 653 and applied to a real drone system. The experiment results show that the overheads of the intra-partition communication are low, while the resources that are assigned to the drone flight-control program are guaranteed through the partitioning.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.4
• /
• pp.901-915
• /
• 1999

Parallel computers are known to be excellent in performance per cost also satisfying scalability and high performance. However parallel machines have enjoyed limited success because of difficulty in parallel programming and non-portability between parallel machines. Recently, researchers have sought to develop data parallel language that provides machine independent programming systems. Data parallel language such as High Performance Fortran provides a basis to write a parallel program based on a global name space by partitioning data and computation, generating message-passing function. In this paper, we describe the Parallel Programming Translator(PPTran), source-to-source data parallel compiler, generating MPI SPMD parallel program from HPF input program through four phases such as data dependence analysis, partitioning data, partitioning computation, and code generation with explicit message-passing and verify the performance of PPTran

• KIPS Transactions on Software and Data Engineering
• /
• v.9 no.11
• /
• pp.377-386
• /
• 2020

Mobile cloud computing involves mobile or embedded devices as clients, and features small devices with constrained resource and low availability. Due to the fast expansion of smart phones and smart peripheral devices, researches on mobile cloud computing attract academia's interest more than ever. Computation offloading, or code offloading, enhances the performance of computation by migrating a part of computation of a mobile system to nearby cloud servers with more computational resources through wired or wireless networks. Code offloading is considered as one of the best approaches overcoming the limited resources of mobile systems. In this paper, we analyze the factors and the performance of code offloading, especially focusing on static program partitioning and data protection. We survey state-of-the-art researches on analyzed topics. We also describe directions for future research.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.3
• /
• pp.53-67
• /
• 1994

This paper describes the design of a high-level synthesis system. SODAS-VP. which automatically generates hardwares executing operation sequences in pipelined fashion.Target architecture and clocking schemes to drive pipelined datapath are determined, and the handling of pipeline hazards which degrade the performance of pipeline is considered. Partitioning of an operation into load, operation, and store stages, each of which is executed in partitiones control step, is performend. Pipelinecl hardware is generated by handling pipeline hazards with internal forwarding or delay insertion techniques in partitioning process and resolving resource conflicts among the partitioned control steps with similarity measure as a priority function in module allocation process. Experimental results show that SODAS-VP generates hardwares that execute faster than those generated by HAL and ALPS systems. SODAS-VP brings improvement in execution speed by 17.1% and 7.4% comparing with HAL and ALPS systems for a MCNC benchmark program, 5th order elliptical wave filter,respectively.

• 한국전산유체공학회:학술대회논문집
• /
• 1998.11a
• /
• pp.147-152
• /
• 1998

2-D flow fields are studied by using a shared memory parallel computer with a parallel flow analysis program which uses domain decomposition method and MPI library for data exchange at overlapped interface. Especially, effects of directional domain decomposition on parallel efficiency are studied for 2-D Lid-Driven cavity flow and flow through square cavity. It is known from the present study that domain decomposition along the main flow direction gives better parallel efficiency in 1-D partitioning than along the other direction. 2-D partitioning, however, is less sensitive to flow directions and gives good parallel efficiency for most of the cases considered.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.65-68
• /
• 2002

The verification of software part and HW/SW interface suffer from the absence of the hardware platform at the end of partitioning and coding phase in design cycle. In this paper we present the design of easy verification for hardware design. Hardware and software engineer can verify their software program and hardware design for a chip that is emulated in proposed verification environment. Besides, designer can easily design the DEMO system.