• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

• 대한교통학회지
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• 제11권1호
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• pp.23-36
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• 1993

The two-lane, two-way highway simulation program(TWOPAS) is evaluated for Korean Highway Capacity Manual Study. TWOPAS program input variables, especially related vehicle performance, traffic flow relationship, car-following model and passing logic are examined and modified through the analysis results of our two-lane, two-way highway traffic characteristics. Simulation outputs with and without modification are compared with the field data. The results show that improved TWOPAS program(TWOPAS KI) is well suitable for simulating our two-lane, two-way highway condition.

• Journal of information and communication convergence engineering
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• 제20권2호
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• pp.137-142
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• 2022

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

• 한국정보처리학회논문지
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• 제5권4호
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• pp.995-1004
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• 1998

본 논문은 LTS 프로세스 명세 검증을 위해 프로토콜의 행위와 상태에 대한 deadlock, livelock, reachability, liveness 검증을 위한 모델 검증기 구현에 대해 기술하였다. Modal mu-calculus를 사용하여 구현된 모델 검증기는 modal logic으로 표현된 프로토콜 특성이 LTS 명세하에서 만족하는지를 자동적으로 검증해 주는 model checking 도구이고 LTS 명세의 Safety와 Liveness 검증에 매우 강력한 성능을 보이는 것을 구현을 통해 실험적으로 증명하였다. 제시된 도구는 Windows NT 환경하에서 IBM PC로 $C^{++}$언어를 사용하여 구현되었다.

• The Journal of Asian Finance, Economics and Business
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• 제7권7호
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• pp.279-291
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• 2020

This study aims to develop the concept of innovation models with the marketing channel construct approach, marketing innovation, product segmentation, and customer insight; as well as improvements to the theory of resource-based combined with the method of service-dominant logic. This study approach is based on quantitative descriptive conducted with three stages of testing scenarios. The first test is the mapping of the innovation model construct through testing the validity and reliability with the moderation of customer orientation variables. The second scenario examines the relationship of influence between the independent variables on the dependent variable of 29 hypothetical analysis equation modeling. The unit of analysis was conducted on 497 SMEs involved in the food and beverage sectors, with the criteria being SMEs must have a rating of 4-5 points on the Go-Food applications software. The results shown that: 1) the construct used to develop an innovative model both directly and via moderation is positive and significant; 2) Through a complicated relationship that involves all components of the variable, it outlines a positive and significant effect except for the path of analysis (μ5). The theoretical and managerial implications state that the service-dominant logic approach and resource-based view theory have extreme reliability and interrelations.

• 한국디지털건축인테리어학회논문집
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• 제6권2호
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• pp.1-8
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• 2006

This study is investigates space syntax theory, developed by Bill Hiller, used for physical analysis and visual access of space and role of spatial configuration based on social logic. it mean computer program analyze physical structure of space and represent by mathematical logic. it used for predict space use and Descriptive of spatial configuration. This method and theory is incompletion for design, but it enough useful tool for architecture and urban design and will be improved. And development of a simple computer program - SSA(Sspace Syntax Analysis) for space syntax analysis and study. SSA is based on convex map analysis and using VISIO software for easily using and development.

• 한국시뮬레이션학회논문지
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• 제17권4호
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• pp.1-9
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• 2008

본 논문은 Programmable Logic Controller(PLC) 시뮬레이션을 하기 위한 공장 모델(Plant Model)을 자동으로 생성하는 절차에 대해 기술한다. PLC 프로그램은 공정을 제어하는 로직에 관한 정보이며 그 자체로 공장 모델에 대한 어떤 정보도 포함하고 있지 않기 때문에 시뮬레이션을 위해서는 PLC 프로그램에 대응하는 공장 모델이 반드시 필요하다. 지금까지 PLC 시뮬레이션을 위한 공장 모델은 사용자가 직접 구축하는 방식으로 모델링 되었으나 이는 많은 노력과 공정로직의 완전한 이해 및 시뮬레이션 지식이 요구된다. 이런 어려움을 극복하기 위해 논문은 PLC 프로그램의 심볼테이블(Symbol table)로부터 공장모델을 자동으로 생성하는 과정을 제안한다. 이를 위해P LC 심볼이 공장 모델의 생성을 위한 정보를 포함시키는 PLC 심볼의 작명 규칙을 제안한다. 입력된 심볼 리스트를 분석함으로써 공장 모델을 자동으로 추출할 수 있으며 간단한 예제 공정을 대상으로 구현해 본다.

• 기술혁신학회지
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• 제16권1호
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• pp.176-198
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• 2013

예비타당성조사는 대규모 신규 공공투자사업에 대한 신중한 접근을 진작하고자 1999년에 도입되었다. 사업 타당성에 대한 결론 도출 시 비용편익분석으로 대변되는 경제적 타당성 분석을 중요시하므로, R&D사업의 분석과 결론 도출에 있어서 다양한 쟁점이 제기되어 왔다. 본 연구에서는 연구개발부문 예비타당성조사에서 표준화하여 적용할 수 있는 사항을 살펴보았으며, 대표질문과 평가항목 간의 상관관계를 통하여 쟁점 도출을 표준화하는 방안을 제시하였다. 그리고 R&D효과 분류와 논리분석의 적용을 통해 분석전략을 표준화하여 R&D투자 의사결정의 합리화에 기여하고자 한다.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2001년도 춘계학술대회 논문집(한국공작기계학회)
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• pp.171-176
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• 2001

This paper describes the methodology of an IEC 1131-3-based control logic generator for the control system design and converting algorithm between programmable languages. The proposed control logic generator is generated based on the software model and common element with data type, variables, POUs(program organization unit) and execution control unit commonly used within programmable languages of IEC 1131-3 Standard. The generation method of object file was proposed on five programmable language based on IECI 131-3. The generation method of object file is represented as following; 1) the generation method using conversion algorithm from LD to IL with FBD(function block diagram), 2) the generation method using C code generation algorithm from SFC using the SFC execution sequence with FBD and ST(structured text). The proposed control logic generator was implemented by Visual C++ and MFC on MS-windows NT 4.0

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제15권3호
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• pp.211-215
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• 2009

프로그래머블 로직 콘트롤러(PLC)가 원자력 계측제어 시스템과 같은 안전 필수 시스템 구현에 많이 사용됨에 따라, PLC 프로그램에 대한 정형검증의 필요가 높아지고 있다. 본 연구에서는 함수 블록 다이어램(FBD)으로 구현된 PLC 프로그램에 대한 자동화된 정형검증 기법을 제안한다. FBD 프로그램을 검증하기 위해서 먼저 FBD 프로그램을 검증언어인 Verilog로 변환하고, 변환된 Verilog모델에 대해 SMV 모델체커를 호출해 모델체킹을 수행한다. 자동화를 위해 FBD Verifier 도구를 개발하였다. FBD Verifier는 FBD 프로그램으로부터 Verilog 모델로의 자동변환 기능뿐 아니라 모델체킹 결과 생성된 반례를 직관적이고 효과적으로 분석할 수 있는 기능 또한 제공한다. 제안된 기법과 도구를 사용해 원전계측제어시스템 개발사업단의 원자로 보호시스템에 대한 방대한 양의 FBD 프로그램을 성공적으로 검증하였다.