• 전자공학회논문지C
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• 제35C권8호
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• pp.33-41
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• 1998

We have designed a high speed and low power 16bit-ELM adder with variable-sized cells uitlizing the fact that the logic depth of lower bit position is less than that of the higher bit position int he conventional ELM architecture. As a result of HSPICE simulation with 0.8.mu.m single-poly double-metal LG CMOS process parameter, out 16bit-ELM adder with variable-sized cells shows the reduction of power-delay-product, which is less than that of the conventional 16bit-ELM adder with reference-sized cells by 19.3%. We optimized the desin with various logic styles including static CMOs, pass-transistor logic and Wang's XOR/XNOR gate. Maximum delay path of an ELM adder depends on the implementation method of S cells and their logic style.

• 대한기계학회논문집A
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• 제27권8호
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• pp.1409-1417
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• 2003

In the 21st century, the concept of remote design and manufacture is strongly required in manufacturing processes to reduce cost and time-to-market. The objective of this paper is the development of an internet-based dimensional verification system for reverse engineering. An inspection client can register measurement data at the developed web server. Collaborators related to the development of a new product can confirm geometrical form from measurement data, check dimensional information and mark up the important parts, as well as make a statement of their views through the Internet. The developed system is realized through the ActiveX-Server architecture. Functions of the dimensional verification module are constructed as ActiveX by using the visual C＋＋ and OpenGL. The usefulness of the developed system is confirmed through a case study.

• KSBB Journal
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• 제29권4호
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• pp.271-277
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• 2014

In this study, crude extract of the seagrass Zostera japonica, and its solvent-partitioned fractions were evaluated for their antioxidant activity. The crude extract was successively fractionated into n-hexane, 85% aqueous methanol (85% aq.MeOH), n-butanol (n-BuOH), and water fractions by liquid-liquid partition. These include DPPH radical scavenging, hydroxyl radical scavenging in HT-1080 cells, peroxynitrite scavenging, and protective effect on DNA damage caused by hydroxyl radicals generated. In all assays, except for DPPH radical, 85% aq.MeOH and n-BuOH fraction showed the strong antioxidant activity. These results suggest that Z. japonica may be used as a potential source of natural antioxidants for the development of cosmetic product or functional food in the future.

• 스마트미디어저널
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• 제3권4호
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• pp.9-15
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• 2014

버츄얼 플랫폼은 SoC를 구성하는 프로세서 코어 및 주변장치들을 소프트웨어로 모델링한 것으로, 현재 국내외 대기업에서는 버츄얼 플랫폼을 활용한 Top-Down 설계 플로우를 기반으로 최적 SW+SoC 융합시스템 구조 설계 및 IP 재활용을 통해 개발한 다양한 플랫폼을 제품 개발에 활용하고 있다. 본 논문에서는 오픈 IP인 OpenRISC 프로세서 코어 기반의 버츄얼 플랫폼을 제안한다. 제안된 버츄얼 플랫폼은 타겟 코드를 호스트 코드로 변환하여 수행하는 코드 변환 기법을 사용하여 약 20 MIPS 급의 고속 에뮬레이션을 지원한다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.291-292
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• 2006

Currently A demand of high precision workpiece is increasing in industry. At present, roundness measuring machine using Air bearing, coordinate measuring machine that are used from measurement station. but these machines will not be able to apply to In-line process. because of like these machine's price are very expensive and measurement time is long. also, the complexity of conventional roundness measurement method based on fourier transform, it makes difficult to development analysis program. This work present new architecture of a Out-diameter measuring system fur analysis of roundness of product. In this system, the influence of table motion errors is minimize by using two LVDT sensor and knife edge contact tip. We are produce a test machine and make an experimenter on Out-diameter of test bearing. The measurement result compared with roundness measuring machine.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1990년도 하계학술대회 논문집
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• pp.521-524
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• 1990

There is an increasing interest in high-speed signal processing in modern telecommunication and consumer electronics applications. HDTV, ISDN. A limiting factor in Op-Amp based analog integrated circuits is the limited useful frequency range. This research program will develop a new CMOS Op-Amp architecture with improved gainband width product. The new design CMOS Op-Amp will achieve up to 100MHz unity gainband width with a 1.5-micron design rule.

• 한국측량학회지
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• 제19권1호
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• pp.77-83
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• 2001

지상사진측량 방법에 의한 도면 작성은 다소의 번거로운 입체영상의 획득 과정과 고가의 해석기기를 바탕으로 한 도화 과정을 필요로 한다. 이에, 본 연구에서는 이러한 영상 해석 과정을 탈피하여 보다 용이한 방법으로 영상을 획득하고 처리하여 대상물에 대한 도면을 작성하고자 하였다. 이를 위해, 단-사진 정사투영 영상을 생성하기 위한 기하보정 시스템을 구축하고 건축물을 대상으로 다양한 워핑 기법을 적용하여 보정 영상들의 성과를 비교·분석하였다. 이로서, 단-사진 기하보정의 수행성을 평가할 수 있었으며 다양한 비-지형 측정 분야에 이의 활용을 기대한다.

• Design & Manufacturing
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• 제2권4호
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• pp.24-31
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• 2008

The productive products are required diversification of product development and advanced for competitiveness. A lot of methods to fix architecture wrapping panels and stone materials are developed in domestic area very much. In this paper, it is very important that a fixing device of slate and molds were developed to reduce the production cost and improve safety. Therefore new model was suggested to reduce manufacturing cost and structure design and FEM analysis were performed to manufacture die press dies for mass production.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• 제20권4호
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• pp.277-293
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• 2016

We develop an efficient numerical method for pricing the Derivative Linked Securities (DLS). The payoff structure of the hybrid DLS consists with a standard 2-Star step-down type ELS and the range accrual product which depends on the number of days in the coupon period that the index stay within the pre-determined range. We assume that the 2-dimensional Geometric Brownian Motion (GBM) as the model of two equities and a no-arbitrage interest model (One-factor Hull and White interest rate model) as a model for the interest rate. In this study, we employ the Monte Carlo simulation method with the Compute Unified Device Architecture (CUDA) parallel computing as the General Purpose computing on Graphic Processing Unit (GPGPU) technology for fast and efficient numerical valuation of DLS. Comparing the Monte Carlo method with single CPU computation or MPI implementation, the result of Monte Carlo simulation with CUDA parallel computing produces higher performance.

• ETRI Journal
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• 제34권2호
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• pp.256-259
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• 2012

The double-base number system has been used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity. This letter proposes an innovative multiplier architecture using hybrid operands. The multiplier can easily be linked to flash analog-to-digital converters or digital systems through a double-base number encoder (DBNE) for realtime signal processing. The design of the DBNE and the multiplier enable faster digital signal processing and require less hardware resources compared to the binary processing method.