• Journal of Broadcast Engineering
• /
• v.12 no.1 s.34
• /
• pp.53-60
• /
• 2007

A Digital Broadcasting Satellite (DBS) receiver converts digital A/V streams received from a satellite to analog NTSC A/V signals in real-time. Multi-tasking is an efficient way to improve the utilization of the processor core in real-time applications. In this paper, we propose a hybrid approach with a balanced trade-off between hardware kernel and multi-tasking programming to increase a system throughput. First, the schedulability of the critical hard real-time tasks in the DBS receiver is verified by using a simple feasibility test. Then, several soft real-time tasks are thoughtfully programmed to satisfy functional requirements of the system.

• The Journal of the Korea Contents Association
• /
• v.17 no.10
• /
• pp.587-597
• /
• 2017

Recently, the demand for real-time performance in mobile environment is increasing due to the improvement of hardware performance, however a GPOS(General-Purpose Operating System) such as Android and Linux do not provide real-time performance. We developed RTiK(Real-Time implant Kernel) for this problem, but it has the disadvantage of supporting only x86 Architecture. In this paper, we designed and implemented a RTiKA(Real-Time implanted Kernel for ARM) to support real-time in ARM Linux. We used MCT(Multi-Core Timer) timer which replaces Local APIC Timer for real-time support, and we measured the period of generated real-time task for performance verification and evaluation. As the recent the RTiKA can guarantee the operating of several real-time tasks based on the cycle of 1ms.

• Journal of KIISE:Information Networking
• /
• v.36 no.2
• /
• pp.118-129
• /
• 2009

The ISO 18000-7 Active RFID standard, a single channel system operating in the 433Mhz, faces technical difficulties in supporting some recently introduced application demands because of its low transmission rates and radio interference between readers. We propose a new multi-channel active RFID system operating in the 2.4Ghz. The special feature of the proposed system is that a reader makes use of multiple interfaces to improve its performance like a multi-core processor. However if only a small part of interfaces are actually used, the performance improvement would not meet the expectation. To overcome this problem, a new multi-channel multi-interface active RFID protocol, which balances communication loads among all available interfaces, is necessary. 3 protocols, named as "Aggregated", "LP-Combined", "AP-Balanced", are proposed. Through simulation, we compare them for various conditions by changing number of tags, number of interfaces, tag data size. AP-Balanced shows the best performance and its performance increases almost linearly as the number of interface increases, which meets our expectation.

• Journal of Korea Multimedia Society
• /
• v.9 no.4
• /
• pp.388-400
• /
• 2006

There are wireless location acquisition technique, LBS platform technique, and LBS application technique in the important technical elements of the LBS. In this paper, we design a location data management system which is the core base technique of the important technical elements of the LBS. The proposed system consist of an application interface of LBS, a query processor of application. service, a location estimator of the moving objects, a location information manager, a real-time data receiver, and a database of location data. This system manages efficiently the location change information of the moving objects using the database technique, suggests some useful inform to the users of LBS, and supports operation and facility of location estimation to process continuous location data of the moving objects. On the basis of location data triggering, this system supplements the problem of the related location data management systems to complement the loss of location data in the environment of real-time.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.24-30
• /
• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• 한국지구물리탐사학회:학술대회논문집
• /
• 2009.10a
• /
• pp.75-80
• /
• 2009

Despite its flexibility to complex geometry, three-dimensional (3D) electromagnetic(EM) modeling schemes using finite element method (FEM) have been faced to practical limitation due to the resulting large system of equations to be solved. An efficient 3D FEM modeling scheme has been developed, which can adopt either direct or iterative solver depending on the problems. The direct solver PARDISO can reduce the computing time remarkably by incorporating parallel computing on multi-core processor systems, which is appropriate for single frequency multi-source configurations. When limited memory, the iterative solver BiCGSTAB(1) can provide fast and stable convergence. Efficient 3D simulations can be performed by choosing an optimum solver depending on the computing environment and the problems to be solved. This modeling includes various types of controlled-sources and can be exploited as an efficient engine for 3D inversion.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.4
• /
• pp.744-751
• /
• 2006

Even many kinds of Internet-based services have been generated due to the great development of the Internet. PSTN still exists in the center of the national infrastructure network and the transit exchanges will be maintained the core roles in PSTN for many years in the future. These transit exchanges often suffer from unexpected overload situation because they have to process Intelligent Network calls and mobile calls additionally as well as POTS (Plain Old Telephone Service). In this paper, we suggest an efficient overload control algorithm for the distributed transit switching system under the various types of call services. We also show that this algorithm can be implemented easily cooperating with the network management control functions. The simulation technique is used to show that the proposed algorithm effectively controls calls and maintains safely the call processor's load under the various kinds of overload situations.

• The Journal of the Korea Contents Association
• /
• v.9 no.3
• /
• pp.9-19
• /
• 2009

In this paper, we propose a novel hardware architecture to facilitate the applicable SoC chip design of H.264/SVC which has a great deal of advancement in the international standardization in recent. Moreover, a new C-model simulator based on the proposed hardware system will be presented to support optimal SoC circuit development. Since the proposed SVC decoder is consist of some hardware engine for processing of major decoding tools and core processor for software processing, the system is simply implemented with the conventional embedded system. To improve the feasibility and applicability, and reduce the decoder complexity, the hardware decoder architecture is constructed with only the consideration of IPPP structure scalability without using the full B-picture. Finally, we present results of decoder hardware implementation and decoded picture to show the effectiveness of the proposed hardware architecture and C-model simulator.

• Journal of Biomedical Engineering Research
• /
• v.41 no.3
• /
• pp.128-137
• /
• 2020

Cardiac electrophysiology studies often use simulation to predict how cardiac will behave under various conditions. To observe the cardiac tissue movement, it needs to use the high--resolution heart mesh with a sophisticated and large number of nodes. The higher resolution mesh is, the more computation time is needed. To improve computation speed and performance, parallel processing using multi-core processes and network computing resources is performed. In this study, we compared the computational speeds of CPU parallelization and GPU parallelization in virtual heart simulation for efficiently calculating a series of ordinary differential equations (ODE) and partial differential equations (PDE) and determined the optimal CPU and GPU parallelization architecture. We used 2D tissue model and 3D ventricular model to compared the computation performance. Then, we measured the time required to the calculation of ODEs and PDEs, respectively. In conclusion, for the most efficient computation, using GPU parallelization rather than CPU parallelization can improve performance by 4.3 times and 2.3 times in calculations of ODEs and PDE, respectively. In CPU parallelization, it is best to use the number of processors just before the communication cost between each processor is incurred.

• Progress in Superconductivity
• /
• v.8 no.2
• /
• pp.181-185
• /
• 2007

For more than two decades Nb trilayer ($Nb/Al_2O_3/Nb$) process has been serving as the most stable fabrication process of the Josephson junction integrated circuits. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipments. In this work, we took an advantage of advanced fabrication equipments in developing a superconducting Arithmetic Logic Unit (ALU) by using Nb trilayers. The ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for $SiO_2$ depositions. Various dry etching techniques were used to define the Josephson junction areas and film pattering processes. Our Nb films were stress free and showed the $T{_c}'s$ of about 9 K. To enhance the step coverage of Nb films we used reverse bias powered DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at up to 5 GHz clock frequency.